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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id 137sm1009039ioc.20.2020.09.28.16.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2020 16:04:56 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 07/10] net: ipa: share field mask values for GSI general interrupt Date: Mon, 28 Sep 2020 18:04:43 -0500 Message-Id: <20200928230446.20561-8-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200928230446.20561-1-elder@linaro.org> References: <20200928230446.20561-1-elder@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The GSI general interrupt is managed by three registers: enable; status; and clear. The three registers have same set of field bits at the same locations. Use a common set of field masks for all three registers to avoid duplication. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 2 +- drivers/net/ipa/gsi_reg.h | 21 ++++++--------------- 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 203d079c481c4..cb676083dfa73 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -271,7 +271,7 @@ static void gsi_irq_enable(struct gsi *gsi) iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); /* Never enable GSI_BREAK_POINT */ - val = GSI_CNTXT_GSI_IRQ_ALL & ~EN_BREAK_POINT_FMASK; + val = GSI_CNTXT_GSI_IRQ_ALL & ~BREAK_POINT_FMASK; iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); } diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index b789e0f866fa0..8e0e9350c3831 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -340,29 +340,20 @@ GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ (0x0001f118 + 0x4000 * (ee)) -#define BREAK_POINT_FMASK GENMASK(0, 0) -#define BUS_ERROR_FMASK GENMASK(1, 1) -#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) - #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ (0x0001f120 + 0x4000 * (ee)) -#define EN_BREAK_POINT_FMASK GENMASK(0, 0) -#define EN_BUS_ERROR_FMASK GENMASK(1, 1) -#define EN_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define EN_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) -#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0) - #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ (0x0001f128 + 0x4000 * (ee)) -#define CLR_BREAK_POINT_FMASK GENMASK(0, 0) -#define CLR_BUS_ERROR_FMASK GENMASK(1, 1) -#define CLR_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define CLR_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) +/* The masks below are used for the general IRQ STTS, EN, and CLR registers */ +#define BREAK_POINT_FMASK GENMASK(0, 0) +#define BUS_ERROR_FMASK GENMASK(1, 1) +#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) +#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) +#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0) #define GSI_CNTXT_INTSET_OFFSET \ GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) -- 2.20.1