From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20E36C4741F for ; Thu, 1 Oct 2020 11:46:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6A1622262 for ; Thu, 1 Oct 2020 11:46:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="h4x2dSm9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731971AbgJALqc (ORCPT ); Thu, 1 Oct 2020 07:46:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731243AbgJALqc (ORCPT ); Thu, 1 Oct 2020 07:46:32 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F38DC0613D0 for ; Thu, 1 Oct 2020 04:46:32 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id b124so4207844pfg.13 for ; Thu, 01 Oct 2020 04:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Rnni/Cv+bQVQlSIzLD2ItMQfmr811sjupc4SJVMgYT4=; b=h4x2dSm9xB03i9BrBBYUdglp+hnHS11/GMAKzhfsa22ngeWuyIxprjf0s1nq1YK1sq mpX/C4RrV/9tP0GGcbSzEaYzOUkcF1pw28cPnY/barzhlWV8geU0q2Qm6Nim+sCc/al+ u8Ox3O01ikON0e/V/h3e3v2ddeNmwER1h7hyBJ8w1byF2/QCzF2OrKcRvGfwRiuHh0ed TainMiIQyOqqLgBYsi8TGXVEW8BDWwW3HVyiP+slhyUUEmcENgou+n+P/KRwohJZWSd1 j6dv63o5mNLwbUAlNmIGHhP+tAAv4tFNVfZ25O6oJY3hfpoC3wclxTVt8VbdAvyQC7Sw Zztw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Rnni/Cv+bQVQlSIzLD2ItMQfmr811sjupc4SJVMgYT4=; b=ccHKhEU43l5O5ZItu2yMVpq64KhhNgUl/thsPlCZhjk7F9N0huUL4IXy7hkYetTuYF B6iJImEIjRlw5gnwqKuZqbKsfsIScQ16uVZbUIE9ElVqpMpkM2gsvC7n7qDmCxktEkI4 OW6k6j4XyaMvz6DvA4GMe2EPyMhnE7RvgyixK9E1WEKrw8u/Uampk0EVzfZUvFkSmAiA VdLlmF/e6hM7rRKIfYj15VH8ytpARgTt7kQysDReCd7qQ9QoN7HI+iX2sZA5a+Klv6l9 BM7pNx92MjOoSt6x9l0Mb2oGxDXWGoU00J7oHjhHoBGfgl/CA5vS+R+DYrZ3Xf2wvede OOHA== X-Gm-Message-State: AOAM532RbrsykmqwuF4Vb85G2/XPMRkjxSYIwaUu6h+Jr2S3EyNv2y2A Y3aYBqdPI+Qvn+nSG7kCbxEH X-Google-Smtp-Source: ABdhPJxguKQqngkdRbxl7frvbumBZvaSZQE16mQOYdDDvdzboLLPSRdsN3CxrUX97jXWhSgIzmsUPA== X-Received: by 2002:a17:902:c394:b029:d2:4ca:2e22 with SMTP id g20-20020a170902c394b02900d204ca2e22mr7074768plg.77.1601552791161; Thu, 01 Oct 2020 04:46:31 -0700 (PDT) Received: from Mani-XPS-13-9360 ([2409:4072:188:5adb:1423:88c1:4321:a364]) by smtp.gmail.com with ESMTPSA id v8sm5865855pgg.58.2020.10.01.04.46.23 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Oct 2020 04:46:30 -0700 (PDT) Date: Thu, 1 Oct 2020 17:16:20 +0530 From: Manivannan Sadhasivam To: Stanimir Varbanov Cc: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Marc Gonzalez Subject: Re: [PATCH v2 5/5] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 Message-ID: <20201001114619.GC3203@Mani-XPS-13-9360> References: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> <20200930150925.31921-6-manivannan.sadhasivam@linaro.org> <507b3d50-6792-60b7-1ccd-f7b3031c20ac@mm-sol.com> <20201001055736.GB3203@Mani-XPS-13-9360> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stan, On Thu, Oct 01, 2020 at 01:57:59PM +0300, Stanimir Varbanov wrote: > Hi Mani, > > On 10/1/20 8:57 AM, Manivannan Sadhasivam wrote: > > Hi Stan, > > > > On Thu, Oct 01, 2020 at 12:46:46AM +0300, Stanimir Varbanov wrote: > >> Hi Mani, > >> > >> On 9/30/20 6:09 PM, Manivannan Sadhasivam wrote: > >>> For SM8250, we need to write the BDF to SID mapping in PCIe controller > >>> register space for proper working. This is accomplished by extracting > >>> the BDF and SID values from "iommu-map" property in DT and writing those > >>> in the register address calculated from the hash value of BDF. In case > >>> of collisions, the index of the next entry will also be written. > >> > >> This describes what the patch is doing. But why? Is that done in the > >> other DWC low-level drivers or this is qcom specialty? > >> > > > > AFAIK, only some NXP SoCs deal with similar kind of mapping but right now > > this is a Qcom only stuff. > > > >>> > >>> For the sake of it, let's introduce a "config_sid" callback and do it > >>> conditionally for SM8250. > >>> > >>> Signed-off-by: Manivannan Sadhasivam > >>> --- > >>> drivers/pci/controller/dwc/Kconfig | 1 + > >>> drivers/pci/controller/dwc/pcie-qcom.c | 138 +++++++++++++++++++++++++ > >>> 2 files changed, 139 insertions(+) > > > > >>> > >>> +static int qcom_pcie_get_iommu_map(struct qcom_pcie *pcie) > >>> +{ > >>> + /* iommu map structure */ > >>> + struct { > >>> + u32 bdf; > >>> + u32 phandle; > >>> + u32 smmu_sid; > >>> + u32 smmu_sid_len; > >>> + } *map; > >>> + struct device *dev = pcie->pci->dev; > >>> + int i, size = 0; > >>> + u32 smmu_sid_base; > >>> + > >>> + of_get_property(dev->of_node, "iommu-map", &size); > >>> + if (!size) > >>> + return 0; > >>> + > >>> + map = kzalloc(size, GFP_KERNEL); > >>> + if (!map) > >>> + return -ENOMEM; > >>> + > >>> + of_property_read_u32_array(dev->of_node, > >>> + "iommu-map", (u32 *)map, size / sizeof(u32)); > >> > >> iommu-map is a standard DT property why we have to parse it manually? > >> > > > > So right now we don't have a way to pass this information from DT. And there > > is no IOMMU API to parse the fields also. We need to extract this information > > to program the hash tables (BDF, SID) as the mapping between BDF and SID is not > > 1:1 in SM8250. > > We used iommu-map for msm8998 see this commit: > > b84dfd175c09888751f501e471fdca346f582e06 > ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes") > The iommu-map property will be present in most of the SoCs as needed for the SMMU translation of DMA transfers. But in the case of SM8250, we need to map the BDF (Bus Device Function) identifier (aka RID) to the SMMU Stream ID (SID) in the PCIe controller, and we get that information from existing iommu-map property. Thanks, Mani > I also Cc-ed Marc if he knows something more. > > > > > Perhaps I can add this information in commit message. > > > -- > regards, > Stan