From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54E70C4363A for ; Mon, 5 Oct 2020 08:50:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BD6720781 for ; Mon, 5 Oct 2020 08:50:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726197AbgJEIuZ (ORCPT ); Mon, 5 Oct 2020 04:50:25 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:46845 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726060AbgJEIuY (ORCPT ); Mon, 5 Oct 2020 04:50:24 -0400 Received: from twspam01.aspeedtech.com (localhost [127.0.0.2] (may be forged)) by twspam01.aspeedtech.com with ESMTP id 09589RRL047791 for ; Mon, 5 Oct 2020 16:09:27 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 09588T6I047498; Mon, 5 Oct 2020 16:08:29 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Oct 2020 16:28:10 +0800 From: "Chia-Wei, Wang" To: , , , , , , , , , , , , , , , CC: Subject: [PATCH v2 2/5] soc: aspeed: Fix LPC register offsets Date: Mon, 5 Oct 2020 16:28:03 +0800 Message-ID: <20201005082806.28899-3-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201005082806.28899-1-chiawei_wang@aspeedtech.com> References: <20201005082806.28899-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 09588T6I047498 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +++--- drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +++++------ 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index 01ed21e8bfee..36faa0618ada 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -17,12 +17,12 @@ #define DEVICE_NAME "aspeed-lpc-ctrl" -#define HICR5 0x0 +#define HICR5 0x80 #define HICR5_ENL2H BIT(8) #define HICR5_ENFWH BIT(10) -#define HICR7 0x8 -#define HICR8 0xc +#define HICR7 0x88 +#define HICR8 0x8c struct aspeed_lpc_ctrl { struct miscdevice miscdev; diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c index f3d8d53ab84d..7ce5c9fcc73c 100644 --- a/drivers/soc/aspeed/aspeed-lpc-snoop.c +++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c @@ -28,26 +28,25 @@ #define NUM_SNOOP_CHANNELS 2 #define SNOOP_FIFO_SIZE 2048 -#define HICR5 0x0 +#define HICR5 0x80 #define HICR5_EN_SNP0W BIT(0) #define HICR5_ENINT_SNP0W BIT(1) #define HICR5_EN_SNP1W BIT(2) #define HICR5_ENINT_SNP1W BIT(3) - -#define HICR6 0x4 +#define HICR6 0x84 #define HICR6_STR_SNP0W BIT(0) #define HICR6_STR_SNP1W BIT(1) -#define SNPWADR 0x10 +#define SNPWADR 0x90 #define SNPWADR_CH0_MASK GENMASK(15, 0) #define SNPWADR_CH0_SHIFT 0 #define SNPWADR_CH1_MASK GENMASK(31, 16) #define SNPWADR_CH1_SHIFT 16 -#define SNPWDR 0x14 +#define SNPWDR 0x94 #define SNPWDR_CH0_MASK GENMASK(7, 0) #define SNPWDR_CH0_SHIFT 0 #define SNPWDR_CH1_MASK GENMASK(15, 8) #define SNPWDR_CH1_SHIFT 8 -#define HICRB 0x80 +#define HICRB 0x100 #define HICRB_ENSNP0D BIT(14) #define HICRB_ENSNP1D BIT(15) -- 2.17.1