From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EEA1C433DF for ; Mon, 12 Oct 2020 08:44:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE8E82076E for ; Mon, 12 Oct 2020 08:44:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727077AbgJLIok (ORCPT ); Mon, 12 Oct 2020 04:44:40 -0400 Received: from mga04.intel.com ([192.55.52.120]:30363 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726335AbgJLIok (ORCPT ); Mon, 12 Oct 2020 04:44:40 -0400 IronPort-SDR: 3gDHK1qGACO3L1qL5uV6KuaX5gzcslfS/ledostsqGM4JzkZ1XcaNWNhM5fHcjtT3CHgYLHxQu SEYlC7qpjzag== X-IronPort-AV: E=McAfee;i="6000,8403,9771"; a="163069460" X-IronPort-AV: E=Sophos;i="5.77,366,1596524400"; d="scan'208";a="163069460" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 01:44:39 -0700 IronPort-SDR: Oeag/SldKSVjyU84dfSbkKvpiGqRhgH37KUfOhMm/VNrUaPbQh16cOaqf8bt/dHP5jEJou3n3l rkz5gKScE6IA== X-IronPort-AV: E=Sophos;i="5.77,366,1596524400"; d="scan'208";a="529872518" Received: from shuo-intel.sh.intel.com (HELO localhost) ([10.239.154.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 01:44:33 -0700 Date: Mon, 12 Oct 2020 16:44:31 +0800 From: Shuo A Liu To: Nick Desaulniers Cc: Peter Zijlstra , Segher Boessenkool , Dave Hansen , Greg Kroah-Hartman , LKML , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Sean Christopherson , Yu Wang , Reinette Chatre , Yakui Zhao , Dan Williams , Fengwei Yin , Zhi Wang , Zhenyu Wang Subject: Re: [PATCH v4 04/17] x86/acrn: Introduce hypercall interfaces Message-ID: <20201012084431.GK1057@shuo-intel.sh.intel.com> References: <20200922114311.38804-1-shuo.a.liu@intel.com> <20200922114311.38804-5-shuo.a.liu@intel.com> <20200927105152.GG88650@kroah.com> <6f9a2b83-6904-2290-6c4f-526672390beb@intel.com> <20200930111612.GZ2628@hirez.programming.kicks-ass.net> <20200930161036.GY28786@gate.crashing.org> <20200930171346.GC2628@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.8.3 (2017-05-23) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 30.Sep'20 at 12:14:03 -0700, Nick Desaulniers wrote: >On Wed, Sep 30, 2020 at 10:13 AM Peter Zijlstra wrote: >> >> On Wed, Sep 30, 2020 at 11:10:36AM -0500, Segher Boessenkool wrote: >> >> > Since this variable is a local register asm, on entry to the asm the >> > compiler guarantees that the value lives in the assigned register (the >> > "r8" hardware register in this case). This all works completely fine. >> > This is the only guaranteed behaviour for local register asm (well, >> > together with analogous behaviour for outputs). >> >> Right, that's what they're trying to achieve. The hypervisor calling >> convention needs that variable in %r8 (which is somewhat unfortunate). >> >> AFAIK this is the first such use in the kernel, but at least the gcc-4.9 >> (our oldest supported version) claims to support this. >> >> So now we need to know if clang will actually do this too.. > >Does clang support register local storage? Let's use godbolt.org to find out: >https://godbolt.org/z/YM45W5 >Looks like yes. You can even check different GCC versions via the >dropdown in the top right. > >The -ffixed-* flags are less well supported in Clang; they need to be >reimplemented on a per-backend basis. aarch64 is relatively well >supported, but other arches not so much IME. > >Do we need register local storage here? > >static inline long bar(unsigned long hcall_id) >{ > long result; > asm volatile("movl %1, %%r8d\n\t" > "vmcall\n\t" > : "=a" (result) > : "ir" (hcall_id) > : ); > return result; >} Yeah, this approach is also mentioned in the changelog. I will change to this way to follow your preference. With an addtional "r8" clobber what Arvind mentioned. Thanks shuo