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[81.185.165.26]) by smtp.gmail.com with ESMTPSA id c14sm315131wrv.12.2020.10.13.10.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 10:28:37 -0700 (PDT) From: Fabien Parent To: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: matthias.bgg@gmail.com, daniel@ffwll.ch, airlied@linux.ie, p.zabel@pengutronix.de, chunkuang.hu@kernel.org, Fabien Parent Subject: [PATCH 1/2] drm/mediatek: mtk_hdmi: move 2 registers address into of_data Date: Tue, 13 Oct 2020 19:28:31 +0200 Message-Id: <20201013172832.4055545-1-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On MT8167, the two registers SYS_CFG1C and SYS_CFG20 don't have the same address as on MT8173. Add OF data in order to store the address of these two registers. Signed-off-by: Fabien Parent --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 45 ++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index a97725680d4e..c70f195c21be 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -36,6 +36,11 @@ #define NCTS_BYTES 7 +struct mtk_hdmi_data { + uint32_t sys_cfg1c; + uint32_t sys_cfg20; +}; + enum mtk_hdmi_clk_id { MTK_HDMI_CLK_HDMI_PIXEL, MTK_HDMI_CLK_HDMI_PLL, @@ -146,6 +151,7 @@ struct hdmi_audio_param { }; struct mtk_hdmi { + const struct mtk_hdmi_data *data; struct drm_bridge bridge; struct drm_bridge *next_bridge; struct drm_connector conn; @@ -244,21 +250,24 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) */ if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled) regmap_update_bits(hdmi->sys_regmap, - hdmi->sys_offset + HDMI_SYS_CFG20, + hdmi->sys_offset + hdmi->data->sys_cfg20, 0x80008005, enable ? 0x80000005 : 0x8000); else arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000, 0, 0, 0, 0, 0, &res); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); } static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); } @@ -274,12 +283,15 @@ static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, HDMI_RST, HDMI_RST); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, HDMI_RST, 0); mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg1c, ANLG_ON, ANLG_ON); } @@ -362,16 +374,19 @@ static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); usleep_range(2000, 4000); - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); } static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) { - regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, + regmap_update_bits(hdmi->sys_regmap, + hdmi->sys_offset + hdmi->data->sys_cfg20, DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, COLOR_8BIT_MODE); } @@ -1733,6 +1748,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev) return -ENOMEM; hdmi->dev = dev; + hdmi->conf = of_device_get_match_data(dev); ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); if (ret) @@ -1813,8 +1829,15 @@ static int mtk_hdmi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume); + +static struct mtk_hdmi_data mt8173_hdmi_driver_data = { + .sys_cfg1c = HDMI_SYS_CFG1C, + .sys_cfg20 = HDMI_SYS_CFG20, +}; + static const struct of_device_id mtk_drm_hdmi_of_ids[] = { - { .compatible = "mediatek,mt8173-hdmi", }, + { .compatible = "mediatek,mt8173-hdmi", + .data = &mt8173_hdmi_driver_data }, {} }; -- 2.28.0