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[81.185.170.199]) by smtp.gmail.com with ESMTPSA id v123sm3297756wme.7.2020.10.20.10.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 10:43:00 -0700 (PDT) From: Fabien Parent To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: matthias.bgg@gmail.com, robh+dt@kernel.org, daniel@ffwll.ch, airlied@linux.ie, p.zabel@pengutronix.de, chunkuang.hu@kernel.org, Fabien Parent Subject: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC Date: Tue, 20 Oct 2020 19:42:47 +0200 Message-Id: <20201020174253.3757771-3-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201020174253.3757771-1-fparent@baylibre.com> References: <20201020174253.3757771-1-fparent@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation for the MT8167 SoC. The SoC needs an additional clock compared to the already supported SoC: mipi26m. Signed-off-by: Fabien Parent --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index f06f24d405a5..10ae6be7225e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,12 +7,13 @@ channel output. Required properties: - compatible: "mediatek,-dsi" -- the supported chips are mt2701, mt7623, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "engine", "digital", and "hs" +- clock-names: must contain "engine", "digital", "hs" + Can optionnally also contain "mipi26m" - phys: phandle link to the MIPI D-PHY controller. - phy-names: must contain "dphy" - port: Output port node with endpoint definitions as described in @@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" -- the supported chips are mt2701, 7623, mt8173 and mt8183. +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- 2.28.0