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[81.185.170.199]) by smtp.gmail.com with ESMTPSA id v123sm3297756wme.7.2020.10.20.10.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 10:43:03 -0700 (PDT) From: Fabien Parent To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: matthias.bgg@gmail.com, robh+dt@kernel.org, daniel@ffwll.ch, airlied@linux.ie, p.zabel@pengutronix.de, chunkuang.hu@kernel.org, Fabien Parent Subject: [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode Date: Tue, 20 Oct 2020 19:42:49 +0200 Message-Id: <20201020174253.3757771-5-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201020174253.3757771-1-fparent@baylibre.com> References: <20201020174253.3757771-1-fparent@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On MT8167, DSI seems to work fine only if we start the clk in HS mode. If we don't start the clk in HS but try to switch later to HS, the display does not work. This commit adds a platform data variable to be used to start the DSI clk in HS mode at power on. Signed-off-by: Fabien Parent --- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 4a188a942c38..461643c05689 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -175,6 +175,7 @@ struct mtk_dsi_driver_data { const u32 reg_cmdq_off; bool has_shadow_ctl; bool has_size_ctl; + bool use_hs_on_power_on; }; struct mtk_dsi { @@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); - mtk_dsi_clk_hs_mode(dsi, 0); + mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on); return 0; err_disable_engine_clk: -- 2.28.0