From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECA0AC55179 for ; Tue, 27 Oct 2020 10:16:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85F0622284 for ; Tue, 27 Oct 2020 10:16:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OV2QY4cw"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2Rz6UZgP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2897713AbgJ0KQg (ORCPT ); Tue, 27 Oct 2020 06:16:36 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:46108 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2897690AbgJ0KQb (ORCPT ); Tue, 27 Oct 2020 06:16:31 -0400 Message-Id: <20201027101349.588965083@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1603793790; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=fhyVmyh5+YCzuIWOCCWmeRkSyPiSgkoPpHYTnro6jTQ=; b=OV2QY4cwJrvCFLZlAx3xvpty170HEeFFfpx0ME3Vm+HLqZyV4gfoxxXNPglyFmKjmKkFOP zuAbW/rk6tqC432lckcvMfgp4kNPKlCql4GX/hej+Jrb0ajNzagFVtLDNUE7SrqUDfDyUQ OaCvB1T5Ow8LCqGuVqu0vTzgrxttFatdzOdwCMIIy8u5ja4GDdQjwRJz8Q3cUxY4MBmxep tnU9TVvvdCAy5bSj7YMhIm+sqrwbBlPWRBsaBdV0MMfP9LArRuCoCLn2k3tE6mI7hW4pXs lqrxABX8puX98MhxNz1aG6m9kF6fQ5dJMRY7NqmgKUoA+mioxFq+hGUovxWuIw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1603793790; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=fhyVmyh5+YCzuIWOCCWmeRkSyPiSgkoPpHYTnro6jTQ=; b=2Rz6UZgP8c2uzphIpNpUOoA8NuDB1mAfG1p4anE5CLai8po5A9Zo26u9awCiF6YSOQHIQA uhHqwZYG5j3hZvAw== Date: Tue, 27 Oct 2020 11:09:51 +0100 From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Sebastian Andrzej Siewior Subject: [patch 2/2] x86/fpu: Make kernel FPU protection RT friendly References: <20201027100949.181320853@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Non RT kernels need to protect FPU against preemption and bottom half processing. This is achieved by disabling bottom halfs via local_bh_disable() which implictly disables preemption. On RT kernels this protection mechanism is not sufficient because local_bh_disable() does not disable preemption. It serializes bottom half related processing via a CPU local lock. As bottom halfs are running always in thread context on RT kernels disabling preemption is the proper choice as it implicitly prevents bottom half processing. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/fpu/api.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -32,15 +32,27 @@ extern void fpregs_mark_activate(void); * * local_bh_disable() protects against both preemption and soft interrupts * on !RT kernels. + * + * On RT kernels local_bh_disable() is not sufficient because it only + * serializes soft interrupt related sections via a local lock, but stays + * preemptible. Disabling preemption is the right choice here as bottom + * half processing is always in thread context on RT kernels so it + * implicitly prevents bottom half processing as well. */ static inline void fpregs_lock(void) { - local_bh_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_bh_disable(); + else + preempt_disable(); } static inline void fpregs_unlock(void) { - local_bh_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_bh_enable(); + else + preempt_enable(); } #ifdef CONFIG_X86_DEBUG_FPU