From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70151C2D0A3 for ; Thu, 29 Oct 2020 07:21:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12F0521D41 for ; Thu, 29 Oct 2020 07:21:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hfMsCFwA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726507AbgJ2HVv (ORCPT ); Thu, 29 Oct 2020 03:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726086AbgJ2HVO (ORCPT ); Thu, 29 Oct 2020 03:21:14 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD92EC0613B1 for ; Thu, 29 Oct 2020 00:21:13 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id f38so1622050pgm.2 for ; Thu, 29 Oct 2020 00:21:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gb8W1h7SGvff5jSaYiQH332H5P74pGN/45rkGwlqp7I=; b=hfMsCFwAQdfDuLjo+Ui7dBZqVsbHG/jetagR8wx8OBrlM/1PbHauX12FHXTGU5YiPD kZSr24MVbUxtsThgqe2VlTZzLAAZYS7RqMwLO16bQoZFMRdJbp7gFDko6u/BQk9+VrpF qyjpYS20tFW1dbYd78w4ogTWEdrC7CMx6HqjxaBfPaStaezjdK2xt2m5Az1tS7nGCLUu bdy3MCWEo8xj7utaxhZN6KezNBzdz+8wGk8pxNvw25DUK6MIESNLUo5Q/4ZG6WneswBL CgXxOxNFYAZam6eH/PW4Nwv0FVk4p7T22zLoBsYFI/hlLaa0y0Jg4Jjpt+N5kKGDX+lA LI8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gb8W1h7SGvff5jSaYiQH332H5P74pGN/45rkGwlqp7I=; b=Dycaa0P/37iyCfDDUWm2vt0vGd3vKt3cM6kSmrU6/oVWvRDu8ebbl/WDLQpQZ12dpN jvd27evkGpPp5JG+kiimiSN28bKPaYGMGwSeGwHD995QmYSsh0L4egNEavSfhJTivci6 1KiMIwzeH3+3dCDDJMBpBsQfy5gADv9bcf5XzCBJMiB1Zuu3fEvrw8HsD/7PrNgor8tO kUSNBmxYn2VNlZoIgvdHfBsk9CCYiYqxwebiJxJ/WLClBfJ9UP0RuuHsCJt2S+RF7FNP p2k9mNZeZgsgIhUcvsiRTp3suaZE966WzKuhnI/ETXhqh7PANpnyrO8fYNtBwhDxZOV1 SBDg== X-Gm-Message-State: AOAM531hc+ghuy4maGLe4F7nnMKQuReNXVkYvezhNQMukLeRH3Jr7p/I fAIegTwBabPiLbfakV2nWeuJcA== X-Google-Smtp-Source: ABdhPJy9IiqQieqB/D06bO7Ti1FeJBIEs1oY69WLBD9Xq3D+lwNRgjv6Td3xc7gyWXRFWlcQ1quPKQ== X-Received: by 2002:a17:90a:b30b:: with SMTP id d11mr2826106pjr.163.1603956073275; Thu, 29 Oct 2020 00:21:13 -0700 (PDT) Received: from localhost ([2600:3c01::f03c:91ff:fe8a:bb03]) by smtp.gmail.com with ESMTPSA id 3sm1818418pfv.92.2020.10.29.00.21.12 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Oct 2020 00:21:12 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andre Przywara , Dave Martin , Wei Li , James Clark , Al Grant , "linux-kernel@vger.kernel.org" Cc: Leo Yan Subject: [PATCH v5 19/21] perf arm-spe: Add more sub classes for operation packet Date: Thu, 29 Oct 2020 15:19:25 +0800 Message-Id: <20201029071927.9308-20-leo.yan@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029071927.9308-1-leo.yan@linaro.org> References: <20201029071927.9308-1-leo.yan@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the operation type packet payload with load/store class, it misses to support these sub classes: - A load/store targeting the general-purpose registers; - A load/store targeting unspecified registers; - The ARMv8.4 nested virtualisation extension can redirect system register accesses to a memory page controlled by the hypervisor. The SPE profiling feature in newer implementations can tag those memory accesses accordingly. Add the bit pattern describing load/store sub classes, so that the perf tool can decode it properly. Inspired by Andre Przywara, refined the commit log and code for more clear description. Co-developed-by: Andre Przywara Signed-off-by: Leo Yan Reviewed-by: Andre Przywara --- .../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index 575635c54e48..70593a4e0aa5 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -326,9 +326,23 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet, arm_spe_pkt_snprintf(&err, &buf, &blen, " EXCL"); if (payload & SPE_OP_PKT_AR) arm_spe_pkt_snprintf(&err, &buf, &blen, " AR"); - } else if (SPE_OP_PKT_LDST_SUBCLASS_GET(payload) == - SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP) { + } + + switch (SPE_OP_PKT_LDST_SUBCLASS_GET(payload)) { + case SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP: arm_spe_pkt_snprintf(&err, &buf, &blen, " SIMD-FP"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_GP_REG: + arm_spe_pkt_snprintf(&err, &buf, &blen, " GP-REG"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG: + arm_spe_pkt_snprintf(&err, &buf, &blen, " UNSPEC-REG"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG: + arm_spe_pkt_snprintf(&err, &buf, &blen, " NV-SYSREG"); + break; + default: + break; } return err ?: (int)(buf_len - blen); -- 2.17.1