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[98.128.180.251]) by smtp.gmail.com with ESMTPSA id 13sm313017lfy.90.2020.11.20.02.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Nov 2020 02:50:08 -0800 (PST) From: Ulf Hansson To: Linus , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ulf Hansson Subject: [GIT PULL] MMC fixes for v5.10-rc5 Date: Fri, 20 Nov 2020 11:50:07 +0100 Message-Id: <20201120105007.8184-1-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, Here's a PR with a couple of MMC fixes intended for v5.10-rc5. Details about the highlights are as usual found in the signed tag. Please pull this in! Kind regards Ulf Hansson The following changes since commit 09162bc32c880a791c6c0668ce0745cf7958f576: Linux 5.10-rc4 (2020-11-15 16:44:31 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git tags/mmc-v5.10-rc4 for you to fetch changes up to d06d60d52ec0b0eef702dd3e7b4699f0b589ad0f: mmc: sdhci-of-arasan: Issue DLL reset explicitly (2020-11-17 12:44:44 +0100) ---------------------------------------------------------------- MMC host: - sdhci-of-arasan: Stabilize communication by fixing tap value configs - sdhci-pci: Use SDR25 timing for HS mode for BYT-based Intel HWs ---------------------------------------------------------------- Adrian Hunter (1): mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers Manish Narani (3): mmc: sdhci-of-arasan: Allow configuring zero tap values mmc: sdhci-of-arasan: Use Mask writes for Tap delays mmc: sdhci-of-arasan: Issue DLL reset explicitly drivers/mmc/host/sdhci-of-arasan.c | 51 ++++++++++++++------------------------ drivers/mmc/host/sdhci-pci-core.c | 13 ++++++++-- 2 files changed, 30 insertions(+), 34 deletions(-)