From: David Brazdil <dbrazdil@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dennis Zhou <dennis@kernel.org>,
Tejun Heo <tj@kernel.org>, Christoph Lameter <cl@linux.com>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Quentin Perret <qperret@google.com>,
Andrew Scull <ascull@google.com>,
Andrew Walbran <qwandor@google.com>,
kernel-team@android.com
Subject: Re: [PATCH v2 04/24] arm64: Move MAIR_EL1_SET to asm/memory.h
Date: Wed, 25 Nov 2020 10:31:37 +0000 [thread overview]
Message-ID: <20201125103137.iml7mqpzhylldvqy@google.com> (raw)
In-Reply-To: <87mtz85geh.wl-maz@kernel.org>
On Mon, Nov 23, 2020 at 01:52:54PM +0000, Marc Zyngier wrote:
> On Mon, 16 Nov 2020 20:42:58 +0000,
> David Brazdil <dbrazdil@google.com> wrote:
> >
> > KVM currently initializes MAIR_EL2 to the value of MAIR_EL1. In
> > preparation for initializing MAIR_EL2 before MAIR_EL1, move the constant
> > into a shared header file. Since it is used for EL1 and EL2, rename to
> > MAIR_ELx_SET.
> >
> > Signed-off-by: David Brazdil <dbrazdil@google.com>
> > ---
> > arch/arm64/include/asm/memory.h | 29 ++++++++++++++---------------
> > arch/arm64/include/asm/sysreg.h | 30 ++++++++++++++++++++++++++++++
> > arch/arm64/mm/proc.S | 15 +--------------
> > 3 files changed, 45 insertions(+), 29 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
> > index cd61239bae8c..8ae8fd883a0c 100644
> > --- a/arch/arm64/include/asm/memory.h
> > +++ b/arch/arm64/include/asm/memory.h
> > @@ -13,6 +13,7 @@
> > #include <linux/const.h>
> > #include <linux/sizes.h>
> > #include <asm/page-def.h>
> > +#include <asm/sysreg.h>
> >
> > /*
> > * Size of the PCI I/O space. This must remain a power of two so that
> > @@ -124,21 +125,6 @@
> > */
> > #define SEGMENT_ALIGN SZ_64K
> >
> > -/*
> > - * Memory types available.
> > - *
> > - * IMPORTANT: MT_NORMAL must be index 0 since vm_get_page_prot() may 'or' in
> > - * the MT_NORMAL_TAGGED memory type for PROT_MTE mappings. Note
> > - * that protection_map[] only contains MT_NORMAL attributes.
> > - */
> > -#define MT_NORMAL 0
> > -#define MT_NORMAL_TAGGED 1
> > -#define MT_NORMAL_NC 2
> > -#define MT_NORMAL_WT 3
> > -#define MT_DEVICE_nGnRnE 4
> > -#define MT_DEVICE_nGnRE 5
> > -#define MT_DEVICE_GRE 6
> > -
> > /*
> > * Memory types for Stage-2 translation
> > */
> > @@ -152,6 +138,19 @@
> > #define MT_S2_FWB_NORMAL 6
> > #define MT_S2_FWB_DEVICE_nGnRE 1
> >
> > +/*
> > + * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
> > + * changed during __cpu_setup to Normal Tagged if the system supports MTE.
> > + */
> > +#define MAIR_ELx_SET \
> > + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
> > +
> > #ifdef CONFIG_ARM64_4K_PAGES
> > #define IOREMAP_MAX_ORDER (PUD_SHIFT)
> > #else
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index e2ef4c2edf06..24e773414cb4 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -635,6 +635,34 @@
> > /* Position the attr at the correct index */
> > #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
> >
> > +/*
> > + * Memory types available.
> > + *
> > + * IMPORTANT: MT_NORMAL must be index 0 since vm_get_page_prot() may 'or' in
> > + * the MT_NORMAL_TAGGED memory type for PROT_MTE mappings. Note
> > + * that protection_map[] only contains MT_NORMAL attributes.
> > + */
> > +#define MT_NORMAL 0
> > +#define MT_NORMAL_TAGGED 1
> > +#define MT_NORMAL_NC 2
> > +#define MT_NORMAL_WT 3
> > +#define MT_DEVICE_nGnRnE 4
> > +#define MT_DEVICE_nGnRE 5
> > +#define MT_DEVICE_GRE 6
> > +
> > +/*
> > + * Default MAIR_ELx. MT_NORMAL_TAGGED is initially mapped as Normal memory and
> > + * changed during __cpu_setup to Normal Tagged if the system supports MTE.
> > + */
> > +#define MAIR_ELx_SET \
> > + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \
> > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
> > +
> > /* id_aa64isar0 */
> > #define ID_AA64ISAR0_RNDR_SHIFT 60
> > #define ID_AA64ISAR0_TLB_SHIFT 56
> > @@ -992,6 +1020,7 @@
> > /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
> > #define SYS_MPIDR_SAFE_VAL (BIT(31))
> >
> > +#ifndef LINKER_SCRIPT
>
> This is terribly ugly. Why is this included by the linker script? Does
> it actually define __ASSEMBLY__?
vmlinux.lds.S includes memory.h for PAGE_SIZE. And yes, linker scripts are
built with this rule:
cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \
-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
I tried a few things and wasn't completely happy with any of them. I think in
the previous spin you suggested moving this constant to sysreg.h. That works
too but sysreg.h seems to have only architecture constants, memory.h about a
Linux-specific configuration, so I wanted to keep it here.
>
> > #ifdef __ASSEMBLY__
> >
> > .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> > @@ -1109,5 +1138,6 @@
> > })
> >
> > #endif
> > +#endif /* LINKER_SCRIPT */
> >
> > #endif /* __ASM_SYSREG_H */
> > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> > index 23c326a06b2d..e3b9aa372b96 100644
> > --- a/arch/arm64/mm/proc.S
> > +++ b/arch/arm64/mm/proc.S
> > @@ -45,19 +45,6 @@
> > #define TCR_KASAN_FLAGS 0
> > #endif
> >
> > -/*
> > - * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
> > - * changed during __cpu_setup to Normal Tagged if the system supports MTE.
> > - */
> > -#define MAIR_EL1_SET \
> > - (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
> > - MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
> > - MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \
> > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
> > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
> > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \
> > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
> > -
> > #ifdef CONFIG_CPU_PM
> > /**
> > * cpu_do_suspend - save CPU registers context
> > @@ -425,7 +412,7 @@ SYM_FUNC_START(__cpu_setup)
> > /*
> > * Memory region attributes
> > */
> > - mov_q x5, MAIR_EL1_SET
> > + mov_q x5, MAIR_ELx_SET
> > #ifdef CONFIG_ARM64_MTE
> > /*
> > * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
> > --
> > 2.29.2.299.gdc1121823c-goog
> >
> >
>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2020-11-25 10:31 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 20:42 [PATCH v2 00/24] Opt-in always-on nVHE hypervisor David Brazdil
2020-11-16 20:42 ` [PATCH v2 01/24] psci: Support psci_ops.get_version for v0.1 David Brazdil
2020-11-16 20:42 ` [PATCH v2 02/24] psci: Accessor for configured PSCI function IDs David Brazdil
2020-11-23 13:47 ` Marc Zyngier
2020-11-16 20:42 ` [PATCH v2 03/24] arm64: Make cpu_logical_map() take unsigned int David Brazdil
2020-11-16 20:42 ` [PATCH v2 04/24] arm64: Move MAIR_EL1_SET to asm/memory.h David Brazdil
2020-11-23 13:52 ` Marc Zyngier
2020-11-25 10:31 ` David Brazdil [this message]
2020-11-25 11:21 ` Marc Zyngier
2020-11-25 13:26 ` David Brazdil
2020-11-25 13:33 ` Marc Zyngier
2020-11-16 20:42 ` [PATCH v2 05/24] kvm: arm64: Initialize MAIR_EL2 using a constant David Brazdil
2020-11-16 20:43 ` [PATCH v2 06/24] kvm: arm64: Move hyp-init params to a per-CPU struct David Brazdil
2020-11-23 14:20 ` Marc Zyngier
2020-11-25 10:39 ` David Brazdil
2020-11-25 10:49 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 07/24] kvm: arm64: Refactor handle_trap to use a switch David Brazdil
2020-11-23 14:32 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 08/24] kvm: arm64: Add SMC handler in nVHE EL2 David Brazdil
2020-11-23 18:00 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 09/24] kvm: arm64: Add .hyp.data..ro_after_init ELF section David Brazdil
2020-11-16 20:43 ` [PATCH v2 10/24] kvm: arm64: Support per_cpu_ptr in nVHE hyp code David Brazdil
2020-11-16 20:43 ` [PATCH v2 11/24] kvm: arm64: Create nVHE copy of cpu_logical_map David Brazdil
2020-11-16 20:43 ` [PATCH v2 12/24] kvm: arm64: Bootstrap PSCI SMC handler in nVHE EL2 David Brazdil
2020-11-23 17:55 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 13/24] kvm: arm64: Add offset for hyp VA <-> PA conversion David Brazdil
2020-11-16 20:43 ` [PATCH v2 14/24] kvm: arm64: Forward safe PSCI SMCs coming from host David Brazdil
2020-11-16 20:43 ` [PATCH v2 15/24] kvm: arm64: Extract parts of el2_setup into a macro David Brazdil
2020-11-23 15:27 ` Marc Zyngier
2020-11-25 12:57 ` David Brazdil
2020-11-16 20:43 ` [PATCH v2 16/24] kvm: arm64: Extract __do_hyp_init into a helper function David Brazdil
2020-11-16 20:43 ` [PATCH v2 17/24] kvm: arm64: Add CPU entry point in nVHE hyp David Brazdil
2020-11-16 20:43 ` [PATCH v2 18/24] kvm: arm64: Add function to enter host from KVM nVHE hyp code David Brazdil
2020-11-16 20:43 ` [PATCH v2 19/24] kvm: arm64: Intercept host's PSCI_CPU_ON SMCs David Brazdil
2020-11-23 17:04 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 20/24] kvm: arm64: Intercept host's CPU_SUSPEND PSCI SMCs David Brazdil
2020-11-23 17:22 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 21/24] kvm: arm64: Add kvm-arm.protected early kernel parameter David Brazdil
2020-11-23 17:30 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 22/24] kvm: arm64: Keep nVHE EL2 vector installed David Brazdil
2020-11-16 20:43 ` [PATCH v2 23/24] kvm: arm64: Trap host SMCs in protected mode David Brazdil
2020-11-23 17:36 ` Marc Zyngier
2020-11-16 20:43 ` [PATCH v2 24/24] kvm: arm64: Fix EL2 mode availability checks David Brazdil
2020-11-23 13:44 ` [PATCH v2 00/24] Opt-in always-on nVHE hypervisor Marc Zyngier
2020-11-23 18:01 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201125103137.iml7mqpzhylldvqy@google.com \
--to=dbrazdil@google.com \
--cc=ascull@google.com \
--cc=catalin.marinas@arm.com \
--cc=cl@linux.com \
--cc=dennis@kernel.org \
--cc=james.morse@arm.com \
--cc=julien.thierry.kdev@gmail.com \
--cc=kernel-team@android.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=maz@kernel.org \
--cc=qperret@google.com \
--cc=qwandor@google.com \
--cc=suzuki.poulose@arm.com \
--cc=tj@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®