From: andy.tang@nxp.com
To: axboe@kernel.dk
Cc: linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org,
Yuantian Tang <andy.tang@nxp.com>
Subject: [PATCH] ahci: qoriq: update the port register settings
Date: Tue, 1 Dec 2020 16:18:41 +0800 [thread overview]
Message-ID: <20201201081841.16228-1-andy.tang@nxp.com> (raw)
From: Yuantian Tang <andy.tang@nxp.com>
The default values for Port register PORT_PHY2 and PORT_PHY3
are better, no need to overwrite them.
The following boards are affected: ls208x, ls1088a, ls1043a,
ls1046a, ls1028a and ls1012a.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
---
drivers/ata/ahci_qoriq.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 5b46fc9aeb4a..896e4dba8500 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -32,8 +32,6 @@
/* port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY2_CFG 0x28184d1f
-#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
@@ -197,8 +195,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
ECC_DIS_ARMV8_CH2,
qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -206,8 +202,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -221,8 +215,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
ECC_DIS_ARMV8_CH2,
qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -238,8 +230,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
ECC_DIS_LS1088A,
qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -247,8 +237,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS2088A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
--
2.17.1
reply other threads:[~2020-12-01 8:11 UTC|newest]
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