From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAAAFC433FE for ; Tue, 8 Dec 2020 14:16:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D32423A77 for ; Tue, 8 Dec 2020 14:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729770AbgLHOQN (ORCPT ); Tue, 8 Dec 2020 09:16:13 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:44308 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbgLHOQN (ORCPT ); Tue, 8 Dec 2020 09:16:13 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kmdm3-00ApGj-QR; Tue, 08 Dec 2020 15:15:27 +0100 Date: Tue, 8 Dec 2020 15:15:27 +0100 From: Andrew Lunn To: Jean Pihet Cc: netdev@vger.kernel.org, LKML , Ryan Barnett , Conrad Ratschan , Hugo Cornelis , Arnout Vandecappelle Subject: Re: [PATCH v2] net: dsa: ksz8795: adjust CPU link to host interface Message-ID: <20201208141527.GI2475764@lunn.ch> References: <20201201083408.51006-1-jean.pihet@newoldbits.com> <20201201184100.GN2073444@lunn.ch> <20201201204516.GA2324545@lunn.ch> <20201208021131.GE2475764@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > Hi Jean > > > > I never said i was too specific to your board. There are other boards > > using different switches like this. This is where the commit message > > is so important. Without understanding Why? it is hard to point you in > > the right direction. > > > > So you setup is: > > > > SoC - MAC - PHY - PHY - MAC - Switch. > > > > The SoC MAC driver is looking after the first PHY? > > No, the connection is at the MAC level, via RGMII but it is missing the MDC/ > MDIO signals. That means we have to fix the auto-neg parameters from the DT. So the PHY is there, but you cannot talk to it? It has strapping resisters to make it auto-neg to the other PHY? Some switches default their CPU port to the maximum speed the port can do. But not all do. It is worth checking that. > On the 4.14 LTS kernel we are working with, the setup of the parameters is done > via adjust_link. Since the phylink conversion adjust_link is not required > anymore, is this correct? 4.14 is dead in terms of development. Anything you contribute needs to be for net-next, and then you need to figure out how to backport it. Using v5.4 will help with that, since it is much closer, and v5.10 will be LTS. Given the change to phylink, you probably want as new a kernel as possible. If you put a fixed-link property in the "CPU" node, phylink should do the right thing for you. Andrew