From: Pratyush Yadav <p.yadav@ti.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 1/3] UBI: Do not zero out EC and VID on ECC-ed NOR flashes
Date: Tue, 8 Dec 2020 23:40:52 +0530 [thread overview]
Message-ID: <20201208181050.z747aiiccoxj6xqz@ti.com> (raw)
In-Reply-To: <20201201102711.8727-2-p.yadav@ti.com>
Richard,
On 01/12/20 03:57PM, Pratyush Yadav wrote:
> For NOR flashes EC and VID are zeroed out before an erase is issued to
> make sure UBI does not mistakenly treat the PEB as used and associate it
> with an LEB.
>
> But on some flashes, like the Cypress Semper S28 SPI NOR flash family,
> multi-pass page programming is not allowed on the default ECC scheme.
> This means zeroing out these magic numbers will result in the flash
> throwing a page programming error.
>
> Do not zero out EC and VID for such flashes. A writesize > 1 is an
> indication of an ECC-ed flash.
Patches 2/3 and 3/3 have been picked up in the spi-nor tree. Can you
please pick this patch up?
--
Regards,
Pratyush Yadav
Texas Instruments India
next prev parent reply other threads:[~2020-12-08 18:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-01 10:27 [PATCH v3 0/3] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it Pratyush Yadav
2020-12-01 10:27 ` [PATCH v3 1/3] UBI: Do not zero out EC and VID on ECC-ed NOR flashes Pratyush Yadav
2020-12-08 18:10 ` Pratyush Yadav [this message]
2020-12-13 23:25 ` Richard Weinberger
2020-12-01 10:27 ` [PATCH v3 2/3] mtd: spi-nor: core: Allow flashes to specify MTD writesize Pratyush Yadav
2020-12-08 16:11 ` Vignesh Raghavendra
2020-12-01 10:27 ` [PATCH v3 3/3] mtd: spi-nor: spansion: Set ECC block size Pratyush Yadav
2020-12-08 16:12 ` Vignesh Raghavendra
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