From: Nishanth Menon <nm@ti.com>
To: Sudeep Holla <sudeep.holla@arm.com>, Suman Anna <s-anna@ti.com>,
Dave Gerlach <d-gerlach@ti.com>
Cc: Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Nishanth Menon <nm@ti.com>
Subject: [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
Date: Wed, 20 Jan 2021 13:51:45 -0600 [thread overview]
Message-ID: <20210120195145.32259-1-nm@ti.com> (raw)
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/
J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/
J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/
Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/
I have'nt split this patch up for fixes tag primarily because the
basic functionality works and this is an improvement than a critical
fixup to backport for older kernels.
arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +-
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index d84c0bc05023..a9fc1af03f27 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 {
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a53-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 66169bcf7c9a..b7005b803149 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 {
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index cc483f7344af..f0587fde147e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 {
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.25.1.377.g2d2118b814c1
next reply other threads:[~2021-01-20 19:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-20 19:51 Nishanth Menon [this message]
2021-01-20 20:49 ` Suman Anna
2021-01-21 10:37 ` Tero Kristo
2021-01-22 12:49 ` Nishanth Menon
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