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From: Yanan Wang <wangyanan55@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, Marc Zyngier <maz@kernel.org>,
	Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	<wanghaibin.wang@huawei.com>, <yezengruan@huawei.com>,
	<zhukeqian1@huawei.com>, <yuzenghui@huawei.com>,
	Yanan Wang <wangyanan55@huawei.com>
Subject: [RFC PATCH v1 1/5] arm64: cpufeature: Detect the ARMv8.4 TTRem feature
Date: Tue, 26 Jan 2021 21:41:58 +0800	[thread overview]
Message-ID: <20210126134202.381996-2-wangyanan55@huawei.com> (raw)
In-Reply-To: <20210126134202.381996-1-wangyanan55@huawei.com>

The ARMv8.4 TTRem feature offers 3 levels of support when changing block
size without changing any other parameters that are listed as requiring
use of break-before-make.

With level 0 supported, software must use break-before-make to avoid the
possible hardware problems. With level 1 supported, besides use of BBM,
software can also make use of the nT block translation entry. With level
2 supported, besides approaches of BBM and nT, software can also directly
change block size, but TLB conflicts possibly occur as a result.

We have found a place where TTRem can be used to improve the performance
in guest stage-2 translation. So detact the TTRem feature here.

Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
---
 arch/arm64/include/asm/cpucaps.h |  3 ++-
 arch/arm64/kernel/cpufeature.c   | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index b77d997b173b..e24570ea7444 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -66,7 +66,8 @@
 #define ARM64_WORKAROUND_1508412		58
 #define ARM64_HAS_LDAPR				59
 #define ARM64_KVM_PROTECTED_MODE		60
+#define ARM64_HAS_ARMv8_4_TTREM			61
 
-#define ARM64_NCAPS				61
+#define ARM64_NCAPS				62
 
 #endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e99eddec0a46..8295dd1d450b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1960,6 +1960,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.min_field_value = ID_AA64ISAR0_TLB_RANGE,
 	},
+	{
+		.desc = "ARMv8.4 TTRem",
+		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+		.capability = ARM64_HAS_ARMv8_4_TTREM,
+		.sys_reg = SYS_ID_AA64MMFR2_EL1,
+		.sign = FTR_UNSIGNED,
+		.field_pos = ID_AA64MMFR2_BBM_SHIFT,
+		.min_field_value = 1,
+		.matches = has_cpuid_feature,
+	},
 #ifdef CONFIG_ARM64_HW_AFDBM
 	{
 		/*
-- 
2.19.1


  reply	other threads:[~2021-01-26 13:44 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-26 13:41 [RFC PATCH v1 0/5] Enable CPU TTRem feature for stage-2 Yanan Wang
2021-01-26 13:41 ` Yanan Wang [this message]
2021-01-26 13:41 ` [RFC PATCH v1 2/5] arm64: cpufeature: Add an API to get level of TTRem supported by hardware Yanan Wang
2021-01-26 13:42 ` [RFC PATCH v1 3/5] KVM: arm64: Support usage of TTRem in guest stage-2 translation Yanan Wang
2021-01-26 13:42 ` [RFC PATCH v1 4/5] KVM: arm64: Add handling of coalescing tables into a block mapping Yanan Wang
2021-01-26 13:42 ` [RFC PATCH v1 5/5] KVM: arm64: Adapt page-table code to new handling of coalescing tables Yanan Wang
2021-01-26 14:18 ` [RFC PATCH v1 0/5] Enable CPU TTRem feature for stage-2 Marc Zyngier

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