From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E602FC433DB for ; Wed, 27 Jan 2021 11:38:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 948512067C for ; Wed, 27 Jan 2021 11:38:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236888AbhA0Lhk (ORCPT ); Wed, 27 Jan 2021 06:37:40 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:11901 "EHLO szxga07-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236978AbhA0Le3 (ORCPT ); Wed, 27 Jan 2021 06:34:29 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4DQhK72fH0z7bnb; Wed, 27 Jan 2021 19:32:11 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.498.0; Wed, 27 Jan 2021 19:33:13 +0800 From: Zhen Lei To: Will Deacon , Robin Murphy , "Mark Rutland" , Joerg Roedel , linux-arm-kernel , iommu , linux-kernel CC: Zhen Lei , Jean-Philippe Brucker , Shameer Kolothum Subject: [PATCH v3 0/3] perf/smmuv3: Don't reserve the PMCG register spaces Date: Wed, 27 Jan 2021 19:32:55 +0800 Message-ID: <20210127113258.1421-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org v2 --> v3: Patch 3 is updated because https://lkml.org/lkml/2021/1/22/532 has been queued in advance. v1 --> v2: According to Robin Murphy's suggestion: https://lkml.org/lkml/2021/1/20/470 Don't reserve the PMCG register spaces, and reserve the entire SMMU register space. v1: Since the PMCG may implement its resigters space(4KB Page0 and 4KB Page1) within the SMMUv3 64KB Page0. In this case, when the SMMUv3 driver reserves the 64KB Page0 resource in advance, the PMCG driver try to reserve its Page0 and Page1 resources, a resource conflict occurs. commit 52f3fab0067d6fa ("iommu/arm-smmu-v3: Don't reserve implementation defined register space") reduce the resource reservation range of the SMMUv3 driver, it only reserves the first 0xe00 bytes in the 64KB Page0, to avoid the above-mentioned resource conflicts. But the SMMUv3.3 add support for ECMDQ, its registers space is also implemented in the SMMUv3 64KB Page0. This means we need to build two separate mappings. New features may be added in the future, and more independent mappings may be required. The simple problem is complicated because the user expects to map the entire SMMUv3 64KB Page0. Therefore, the proper solution is: If the PMCG register resources are located in the 64KB Page0 of the SMMU, the PMCG driver does not reserve the conflict resources when the SMMUv3 driver has reserved the conflict resources before. Instead, the PMCG driver only performs devm_ioremap() to ensure that it can work properly. Zhen Lei (3): perf/smmuv3: Don't reserve the PMCG register spaces perf/smmuv3: Add a MODULE_SOFTDEP() to indicate dependency on SMMU iommu/arm-smmu-v3: Reserving the entire SMMU register space drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24 ++++-------------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 -- drivers/perf/arm_smmuv3_pmu.c | 28 ++++++++++++++++++++++++++-- 3 files changed, 30 insertions(+), 24 deletions(-) -- 1.8.3