From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>
Cc: "Jernej Skrabec" <jernej.skrabec@siol.net>,
"Samuel Holland" <samuel@sholland.org>,
"Icenowy Zheng" <icenowy@aosc.io>,
"Rob Herring" <robh@kernel.org>,
"Clément Péron" <peron.clem@gmail.com>,
"Shuosheng Huang" <huangshuosheng@allwinnertech.com>,
"Yangtao Li" <tiny.windzz@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
"Alexandre Torgue" <alexandre.torgue@st.com>,
"David S . Miller" <davem@davemloft.net>,
"Giuseppe Cavallaro" <peppe.cavallaro@st.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Jose Abreu" <joabreu@synopsys.com>,
netdev@vger.kernel.org
Subject: [PATCH v5 16/20] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register
Date: Wed, 27 Jan 2021 17:24:56 +0000 [thread overview]
Message-ID: <20210127172500.13356-17-andre.przywara@arm.com> (raw)
In-Reply-To: <20210127172500.13356-1-andre.przywara@arm.com>
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 58e0511badba..c7951790ed98 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1124,11 +1124,13 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
struct stmmac_resources stmmac_res;
struct sunxi_priv_data *gmac;
struct device *dev = &pdev->dev;
+ struct reg_field syscon_field;
phy_interface_t interface;
int ret;
struct stmmac_priv *priv;
struct net_device *ndev;
struct regmap *regmap;
+ u32 syscon_idx = 0;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
if (ret)
@@ -1190,8 +1192,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
return ret;
}
- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
- *gmac->variant->syscon_field);
+ syscon_field = *gmac->variant->syscon_field;
+ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+ &syscon_idx);
+ if (!ret)
+ syscon_field.reg += syscon_idx * sizeof(u32);
+ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
if (IS_ERR(gmac->regmap_field)) {
ret = PTR_ERR(gmac->regmap_field);
dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1263,6 +1269,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = &emac_variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = &emac_variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac",
+ .data = &emac_variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.17.5
next prev parent reply other threads:[~2021-01-27 17:34 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 17:24 [PATCH v5 00/20] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2021-01-27 17:24 ` [PATCH v5 01/20] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara
2021-01-27 17:24 ` [PATCH v5 02/20] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara
2021-01-27 17:24 ` [PATCH v5 03/20] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara
2021-01-27 17:24 ` [PATCH v5 04/20] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Andre Przywara
2021-01-28 10:15 ` Maxime Ripard
2021-02-02 7:55 ` [linux-sunxi] " Chen-Yu Tsai
2021-02-02 10:11 ` Andre Przywara
2021-02-05 21:56 ` Rob Herring
2021-01-27 17:24 ` [PATCH v5 05/20] Input: axp20x-pek: Bail out if AXP has no interrupt line connected Andre Przywara
2021-01-27 19:42 ` Dmitry Torokhov
2021-01-28 11:11 ` Andre Przywara
2021-01-28 11:36 ` Mark Brown
2021-01-28 12:31 ` Andre Przywara
2021-01-28 15:05 ` Mark Brown
2021-01-27 17:24 ` [PATCH v5 06/20] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara
2021-01-28 10:15 ` Maxime Ripard
2021-02-02 7:58 ` [linux-sunxi] " Chen-Yu Tsai
2021-02-02 8:12 ` Lee Jones
2021-01-27 17:24 ` [PATCH v5 07/20] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara
2021-01-27 17:24 ` [PATCH v5 08/20] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara
2021-01-27 17:24 ` [PATCH v5 09/20] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara
2021-01-27 17:24 ` [PATCH v5 10/20] dt-bindings: i2c: mv64xxx: " Andre Przywara
2021-01-28 8:44 ` Wolfram Sang
2021-01-27 17:24 ` [PATCH v5 11/20] dt-bindings: media: IR: Add H616 IR " Andre Przywara
2021-01-27 17:24 ` [PATCH v5 12/20] dt-bindings: rtc: sun6i: Add H616 " Andre Przywara
2021-01-28 10:20 ` Maxime Ripard
[not found] ` <1675074.8rG671tKPg@kista>
2021-02-02 0:05 ` Andre Przywara
2021-01-27 17:24 ` [PATCH v5 13/20] dt-bindings: spi: sunxi: " Andre Przywara
2021-01-27 17:24 ` [PATCH v5 14/20] dt-bindings: bus: rsb: " Andre Przywara
2021-02-02 7:57 ` Chen-Yu Tsai
2021-01-27 17:24 ` [PATCH v5 15/20] dt-bindings: net: sun8i-emac: " Andre Przywara
2021-01-28 10:21 ` Maxime Ripard
2021-02-05 21:58 ` Rob Herring
2021-01-27 17:24 ` Andre Przywara [this message]
2021-01-28 10:21 ` [PATCH v5 16/20] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Maxime Ripard
2021-01-27 17:24 ` [PATCH v5 17/20] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Andre Przywara
2021-01-27 17:24 ` [PATCH v5 18/20] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2021-01-27 17:24 ` [PATCH v5 19/20] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara
2021-01-27 17:25 ` [PATCH v5 20/20] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara
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