From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16C85C433E0 for ; Thu, 4 Feb 2021 00:04:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1C3364E27 for ; Thu, 4 Feb 2021 00:04:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233875AbhBDAEP (ORCPT ); Wed, 3 Feb 2021 19:04:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234199AbhBDACw (ORCPT ); Wed, 3 Feb 2021 19:02:52 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEE54C061355 for ; Wed, 3 Feb 2021 16:01:47 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id k7so1525416ybm.13 for ; Wed, 03 Feb 2021 16:01:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=KVbXCJbK0fJijUMIx8v2OVwCZqQe15lsxZFi3EGecaw=; b=opyX1IcsdheLOecVRr/E17VB+hX2+bRSNpQU2AKEc75rEOAphJBR1E1zZy11OX5E8D MOTT02kX8RMf1rsG08QGYhs16gYkz9lFqyJk8+BOPm8+Fnsym4JEIPdCulxfA3/o6hOO Oy2BwhKqbLF9w41MIN6AzwhHKh5OEqYySOdgTcqIwdS7nUhb2tZxvHkSmShe3Gj8RluJ ZDJPPvN+CHnmO/xr0U1BwVrx5baf5SYStCy5+yecsF8hrnw7+COuLPAi8sNn4eAEp03b O1fv9qtQrbty3PKFo5Ou+01ZLLblZAEs/V/LxPfsw/fR3nl8V66vPOO4NSXle1B1I4La Ha2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=KVbXCJbK0fJijUMIx8v2OVwCZqQe15lsxZFi3EGecaw=; b=Pt5cXDaYkrrKo74Ah0eytKuqn1abisqyP7yP2bbsmxQhfhJSx1k6UY3vNRt1I/AOce bj6N1etCbZqByfiSPQE7zOBpJoxfXmYAeaqcPm1VRaEIfP2P9RHlyelk7Mon4gOXmZJv ezkLWSPFAQ0iCtaekk0O21PB7KvHEsaWI22ZbRDsdVjlE6UpfaeWUboUU6mK3cWwX3xZ TyahEz7xVU91Vp8wggMTbX4qxZaxy5TrFGgOGH/Wpr7OT3J1rOs37WD0TK88UUusRC5p 07/JgKBhByFEHoILKz07MGwTI9kU92CrjwDuDWkJEP7X4t4oc9BSinZCqqdBc/5zTRIH vj1Q== X-Gm-Message-State: AOAM5329ZQwBfM3AenCQ5oPXPBtJKzah4z5cEmO1S8KlCWGr4AGdsN2B OAmyqc9GTqHW2o9UmQVk0ygHrm+mTD0= X-Google-Smtp-Source: ABdhPJxipC1uw+bK0spQZBfo0QAzIqcG0dWoBMYMahZvik96ZGpn2SfwdWjogVk+rzl+XSv5RRPwRYioj3Q= Sender: "seanjc via sendgmr" X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:a9a0:e924:d161:b6cb]) (user=seanjc job=sendgmr) by 2002:a25:a527:: with SMTP id h36mr8036454ybi.400.1612396907131; Wed, 03 Feb 2021 16:01:47 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 3 Feb 2021 16:01:14 -0800 In-Reply-To: <20210204000117.3303214-1-seanjc@google.com> Message-Id: <20210204000117.3303214-10-seanjc@google.com> Mime-Version: 1.0 References: <20210204000117.3303214-1-seanjc@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 09/12] KVM: x86/mmu: Add helper to generate mask of reserved HPA bits From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Lendacky , Brijesh Singh , Rick Edgecombe Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a helper to generate the mask of reserved PA bits in the host. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/mmu/mmu.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index d462db3bc742..86af58294272 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4123,6 +4123,11 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, vcpu->arch.reserved_gpa_bits, execonly); } +static inline u64 reserved_hpa_bits(void) +{ + return rsvd_bits(shadow_phys_bits, 63); +} + /* * the page table on host is the shadow page table for the page * table in guest or amd nested guest, its mmu features completely @@ -4142,7 +4147,7 @@ reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) */ shadow_zero_check = &context->shadow_zero_check; __reset_rsvds_bits_mask(vcpu, shadow_zero_check, - rsvd_bits(shadow_phys_bits, 63), + reserved_hpa_bits(), context->shadow_root_level, uses_nx, guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), is_pse(vcpu), true); @@ -4179,14 +4184,13 @@ reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, if (boot_cpu_is_amd()) __reset_rsvds_bits_mask(vcpu, shadow_zero_check, - rsvd_bits(shadow_phys_bits, 63), + reserved_hpa_bits(), context->shadow_root_level, false, boot_cpu_has(X86_FEATURE_GBPAGES), true, true); else __reset_rsvds_bits_mask_ept(shadow_zero_check, - rsvd_bits(shadow_phys_bits, 63), - false); + reserved_hpa_bits(), false); if (!shadow_me_mask) return; @@ -4206,7 +4210,7 @@ reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context, bool execonly) { __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, - rsvd_bits(shadow_phys_bits, 63), execonly); + reserved_hpa_bits(), execonly); } #define BYTE_MASK(access) \ -- 2.30.0.365.g02bc693789-goog