From: Heiko Stuebner <heiko@sntech.de>
To: heiko@sntech.de
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Subject: [PATCH 4/5] clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
Date: Fri, 5 Feb 2021 12:05:01 +0100 [thread overview]
Message-ID: <20210205110502.1850669-4-heiko@sntech.de> (raw)
In-Reply-To: <20210205110502.1850669-1-heiko@sntech.de>
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Export the vip-out clock via the newly added clock-id.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 76fb04120089..61413be48d1a 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -474,7 +474,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(4), 5, GFLAGS),
- COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
+ COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
--
2.29.2
next prev parent reply other threads:[~2021-02-06 0:33 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 11:04 [PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 " Heiko Stuebner
2021-02-05 11:04 ` [PATCH 2/5] clk: rockchip: use " Heiko Stuebner
2021-02-05 11:05 ` [PATCH 3/5] clk: rockchip: add clock id for SCLK_VIP_OUT " Heiko Stuebner
2021-02-05 11:05 ` Heiko Stuebner [this message]
2021-02-05 11:05 ` [PATCH 5/5] clk: rockchip: fix DPHY gate locations " Heiko Stuebner
2021-02-06 0:06 ` [PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 " Heiko Stuebner
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