From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A39AEC433DB for ; Wed, 10 Feb 2021 14:12:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60A9064E87 for ; Wed, 10 Feb 2021 14:12:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231984AbhBJOMN (ORCPT ); Wed, 10 Feb 2021 09:12:13 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:24173 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231866AbhBJOLT (ORCPT ); Wed, 10 Feb 2021 09:11:19 -0500 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 11AEARK8031428; Wed, 10 Feb 2021 06:10:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=0oNZfFPSPI7qXXMHtz5R4nxV70W2GWek2APnlNw4wlA=; b=JDuq0VuSctLPJXSCLBc15PvnFTMh2yBjayAaSNT7GQ9SPohgurWC3CEGCIZu5pCq2Dvs dWU1M009JnG3gjZYG1+FfBKCXo4TUmXIm58n/d64xH6EIrXkL0l5ZA69Z9jWurz9mndG E6LMhF4X7sGaQfWf9muW1PXbcCuMNn8GbusDraWphtSgUGNbYP4zbnHt/jn85vEPdHI1 5K3oPVwrWEk+91tlJNYUx68B9SbN0VXJWmTLlGrlNLeu27BzPpTO74uZLzHXi4+HLcO8 dszN5t4K9HzAZ96A4slptbLsPqTQctd49P1qTB1ODNa6d1QT+B/c8fcA55g0WoVOGz53 NQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 36hugqbs0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 10 Feb 2021 06:10:25 -0800 Received: from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 10 Feb 2021 06:10:17 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 10 Feb 2021 06:10:17 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 10 Feb 2021 06:10:17 -0800 Received: from octopus.marvell.com (octopus.marvell.com [10.5.24.3]) by maili.marvell.com (Postfix) with ESMTP id D79483F7041; Wed, 10 Feb 2021 06:10:13 -0800 (PST) From: To: , , CC: , , , , , , , , , , "Konstantin Porotchkin" Subject: [PATCH v2 06/12] arm64: dts: marvell: armada-3270-espressobin: add comphy references Date: Wed, 10 Feb 2021 16:09:43 +0200 Message-ID: <20210210140949.32515-7-kostap@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210210140949.32515-1-kostap@marvell.com> References: <20210210140949.32515-1-kostap@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.737 definitions=2021-02-10_05:2021-02-10,2021-02-10 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Grzegorz Jaszczyk Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Konstantin Porotchkin --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index daffe136c523..bbd955909813 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -59,6 +59,8 @@ /* J9 */ &pcie0 { status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&comphy1 0>; pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; @@ -139,6 +141,9 @@ /* J7 */ &usb3 { status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&comphy0 0>; + phy-names = "usb"; }; /* J8 */ -- 2.17.1