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[71.237.100.236]) by smtp.gmail.com with ESMTPSA id e2sm5451041iov.26.2021.02.26.07.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 07:51:55 -0800 (PST) Date: Fri, 26 Feb 2021 08:51:53 -0700 From: Jordan Crouse To: Sai Prakash Ranjan Cc: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , Bjorn Andersson , linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCHv2 2/2] iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier Message-ID: <20210226155153.hzcesc2gr2qmleh2@cosmicpenguin.net> Mail-Followup-To: Sai Prakash Ranjan , Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , Bjorn Andersson , linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 26, 2021 at 03:25:40PM +0530, Sai Prakash Ranjan wrote: > Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU > both implement "arm,mmu-500" in some QTI SoCs and to run through > adreno smmu specific implementation such as enabling split pagetables > support, we need to match the "qcom,adreno-smmu" compatible first > before apss smmu or else we will be running apps smmu implementation > for adreno smmu and the additional features for adreno smmu is never > set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps > and adreno smmu implementing "arm,mmu-500", so the adreno smmu > implementation is never reached because the current sequence checks > for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that > specific impl and we never reach adreno smmu specific implementation. > > Suggested-by: Akhil P Oommen Acked-by: Jordan Crouse > Signed-off-by: Sai Prakash Ranjan > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bea3ee0dabc2..03f048aebb80 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > { > const struct device_node *np = smmu->dev->of_node; > > - if (of_match_node(qcom_smmu_impl_of_match, np)) > - return qcom_smmu_create(smmu, &qcom_smmu_impl); > - > + /* > + * Do not change this order of implementation, i.e., first adreno > + * smmu impl and then apss smmu since we can have both implementing > + * arm,mmu-500 in which case we will miss setting adreno smmu specific > + * features if the order is changed. > + */ > if (of_device_is_compatible(np, "qcom,adreno-smmu")) > return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > > + if (of_match_node(qcom_smmu_impl_of_match, np)) > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > + > return smmu; > } > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu