From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7399CC433DB for ; Wed, 3 Mar 2021 16:22:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AC9964EEA for ; Wed, 3 Mar 2021 16:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346540AbhCCQSC (ORCPT ); Wed, 3 Mar 2021 11:18:02 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:33774 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233792AbhCCLnO (ORCPT ); Wed, 3 Mar 2021 06:43:14 -0500 Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:2035:1dcd:21c7:b3af]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 404B71F45C2C; Wed, 3 Mar 2021 11:40:28 +0000 (GMT) From: Benjamin Gaignard To: ezequiel@collabora.com, p.zabel@pengutronix.de, mchehab@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, gregkh@linuxfoundation.org, mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, jernej.skrabec@siol.net, peng.fan@nxp.com, hverkuil-cisco@xs4all.nl, dan.carpenter@oracle.com Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v4 10/11] dt-bindings: media: nxp,imx8mq-vpu: Update bindings Date: Wed, 3 Mar 2021 12:39:51 +0100 Message-Id: <20210303113952.178519-11-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303113952.178519-1-benjamin.gaignard@collabora.com> References: <20210303113952.178519-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current bindings seem to make the assumption that the two VPUs hardware blocks (G1 and G2) are only one set of registers. After implementing the VPU reset driver and G2 decoder driver it shows that all the VPUs are independent and don't need to know about the registers of the other blocks. Remove from the bindings the need to set all blocks register but keep reg-names property because removing it from the driver may affect other variants. Signed-off-by: Benjamin Gaignard --- version 4: - rebase the change on top of VPU reset patches: https://www.spinics.net/lists/arm-kernel/msg878440.html version 2: - be more verbose about why I change the bindings Keep in mind that series comes after: https://www.spinics.net/lists/arm-kernel/msg875766.html without that review and ack it won't work .../bindings/media/nxp,imx8mq-vpu.yaml | 46 ++++++++++++------- 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index fd53a4e43572..468435c70eef 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -15,23 +15,25 @@ description: properties: compatible: - const: nxp,imx8mq-vpu + enum: + - nxp,imx8mq-vpu + - nxp,imx8mq-vpu-g2 reg: - maxItems: 2 + maxItems: 1 reg-names: - items: - - const: g1 - - const: g2 + enum: + - g1 + - g2 interrupts: - maxItems: 2 + maxItems: 1 interrupt-names: - items: - - const: g1 - - const: g2 + enum: + - g1 + - g2 clocks: maxItems: 3 @@ -66,14 +68,12 @@ examples: #include #include - vpu: video-codec@38300000 { + vpu_g1: video-codec@38300000 { compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>; - reg-names = "g1", "g2"; - interrupts = , - ; - interrupt-names = "g1", "g2"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = ; + interrupt-names = "g1"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; @@ -81,3 +81,17 @@ examples: power-domains = <&pgc_vpu>; resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>; }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names = "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "g2", "bus"; + power-domains = <&pgc_vpu>; + resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G2>; + }; -- 2.25.1