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Fri, 12 Mar 2021 08:55:16 +0000 From: Suravee Suthikulpanit To: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, Jon.Grimm@amd.com, Wei.Huang2@amd.com, Suravee Suthikulpanit Subject: [RFC PATCH 3/7] iommu/amd: Decouple the logic to enable PPR and GT Date: Fri, 12 Mar 2021 03:04:07 -0600 Message-Id: <20210312090411.6030-4-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210312090411.6030-1-suravee.suthikulpanit@amd.com> References: <20210312090411.6030-1-suravee.suthikulpanit@amd.com> Content-Type: text/plain X-Originating-IP: [165.204.78.2] X-ClientProxiedBy: SN7PR04CA0040.namprd04.prod.outlook.com (2603:10b6:806:120::15) To BYAPR12MB4597.namprd12.prod.outlook.com (2603:10b6:a03:10b::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ethanolx5673host.amd.com (165.204.78.2) by SN7PR04CA0040.namprd04.prod.outlook.com (2603:10b6:806:120::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3912.18 via Frontend Transport; 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This is no longer the case since the IOMMU v2 page table can be enabled without PRR support (for DMA-API use case). Therefore, separate the enabling logic for PPR and GT. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 9126efcbaf2c..5def566de6f6 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -898,14 +898,6 @@ static void iommu_enable_xt(struct amd_iommu *iommu) #endif /* CONFIG_IRQ_REMAP */ } -static void iommu_enable_gt(struct amd_iommu *iommu) -{ - if (!iommu_feature(iommu, FEATURE_GT)) - return; - - iommu_feature_enable(iommu, CONTROL_GT_EN); -} - /* sets a specific bit in the device table entry. */ static void set_dev_entry_bit(u16 devid, u8 bit) { @@ -1882,6 +1874,7 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) amd_iommu_max_glx_val = glxval; else amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); + iommu_feature_enable(iommu, CONTROL_GT_EN); } if (iommu_feature(iommu, FEATURE_GT) && @@ -2530,21 +2523,19 @@ static void early_enable_iommus(void) #endif } -static void enable_iommus_v2(void) +static void enable_iommus_ppr(void) { struct amd_iommu *iommu; - for_each_iommu(iommu) { + for_each_iommu(iommu) iommu_enable_ppr_log(iommu); - iommu_enable_gt(iommu); - } } static void enable_iommus(void) { early_enable_iommus(); - enable_iommus_v2(); + enable_iommus_ppr(); } static void disable_iommus(void) @@ -2935,7 +2926,7 @@ static int __init state_next(void) register_syscore_ops(&amd_iommu_syscore_ops); ret = amd_iommu_init_pci(); init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; - enable_iommus_v2(); + enable_iommus_ppr(); break; case IOMMU_PCI_INIT: ret = amd_iommu_enable_interrupts(); -- 2.17.1