From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: <lgirdwood@gmail.com>, <broonie@kernel.org>, <perex@perex.cz>,
<tiwai@suse.com>, <kuninori.morimoto.gx@renesas.com>,
<peter.ujfalusi@ti.com>, <gustavoars@kernel.org>,
<pierre-louis.bossart@linux.intel.com>, <daniel.baluta@nxp.com>,
<patches@opensource.cirrus.com>, <alsa-devel@alsa-project.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips
Date: Tue, 23 Mar 2021 09:59:29 +0000 [thread overview]
Message-ID: <20210323095929.GS106851@ediswmail.ad.cirrus.com> (raw)
In-Reply-To: <1616150926-22892-1-git-send-email-shengjiu.wang@nxp.com>
On Fri, Mar 19, 2021 at 06:48:46PM +0800, Shengjiu Wang wrote:
> The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz
> and sample rate is 44100Hz, with the configuration pllprescale=2,
> postscale=sysclkdiv=1, some chip may have wrong bclk
> and lrclk output with pll enabled in master mode, but with the
> configuration pllprescale=1, postscale=2, the output clock is correct.
>
> >From Datasheet, the PLL performs best when f2 is between
> 90MHz and 100MHz when the desired sysclk output is 11.2896MHz
> or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice.
>
> So search available sysclk_divs from 2 to 1 other than from 1 to 2.
>
> Fixes: 84fdc00d519f ("ASoC: codec: wm9860: Refactor PLL out freq search")
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Thanks,
Charles
next prev parent reply other threads:[~2021-03-23 10:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 10:48 Shengjiu Wang
2021-03-23 9:59 ` Charles Keepax [this message]
2021-03-23 22:12 ` Mark Brown
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