From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4419C433E0 for ; Tue, 30 Mar 2021 13:07:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 983EB619C8 for ; Tue, 30 Mar 2021 13:07:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232172AbhC3NGy (ORCPT ); Tue, 30 Mar 2021 09:06:54 -0400 Received: from foss.arm.com ([217.140.110.172]:60836 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232169AbhC3NGp (ORCPT ); Tue, 30 Mar 2021 09:06:45 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D47F131B; Tue, 30 Mar 2021 06:06:44 -0700 (PDT) Received: from lpieralisi (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7A883F694; Tue, 30 Mar 2021 06:06:43 -0700 (PDT) Date: Tue, 30 Mar 2021 14:06:37 +0100 From: Lorenzo Pieralisi To: Marc Zyngier Cc: Lecopzer Chen , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, lecopzer@gmail.com, yj.chiang@mediatek.com, Julien Thierry Subject: Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600 Message-ID: <20210330130637.GA26263@lpieralisi> References: <20210330100619.24747-1-lecopzer.chen@mediatek.com> <87o8f1q6c6.wl-maz@kernel.org> <20210330110546.GA24881@lpieralisi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210330110546.GA24881@lpieralisi> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote: > On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote: > > [+Lorenzo, +Julien on an actual email address] > > > > On Tue, 30 Mar 2021 11:06:19 +0100, > > Lecopzer Chen wrote: > > > > > > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ > > > by byte ops, and this doesn't work in GIC-600. > > > > > > We have asked ARM Support [1]: > > > > Please refer to following description in > > > > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for > > > > the GIC600 ACE-lite slave interface supported sizes: > > > > "The GIC-600 only accepts single beat accesses of the sizes for > > > > each register that are shown in the Programmers model, > > > > see Chapter 4 Programmer's model on page 4-102. > > > > All other accesses are rejected and given either an > > > > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.". > > > > > > Thus the register needs to be written by double word operation and > > > the step will be: read 32bit, set byte and write it back. > > > > > > [1] https://services.arm.com/support/s/case/5003t00001L4Pba > > > > You do realise that this link: > > > > - is unusable for most people as it is behind a registration interface > > - discloses confidential information to other people > > > > I strongly suggest you stop posting such links. > > > > > > > > Signed-off-by: Lecopzer Chen > > > --- > > > drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++- > > > 1 file changed, 12 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > > index eb0ee356a629..cfc5a6ad30dc 100644 > > > --- a/drivers/irqchip/irq-gic-v3.c > > > +++ b/drivers/irqchip/irq-gic-v3.c > > > @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio) > > > { > > > void __iomem *base = gic_dist_base(d); > > > u32 offset, index; > > > + u32 val, prio_offset_mask, prio_offset_shift; > > > > > > offset = convert_offset_index(d, GICD_IPRIORITYR, &index); > > > > > > - writeb_relaxed(prio, base + offset + index); > > > + /* > > > + * GIC-600 memory mapping register doesn't support byte opteration, > > > + * thus read 32-bits from register, set bytes and wtire back to it. > > > + */ > > > + prio_offset_shift = (index & 0x3) * 8; > > > + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift); > > > + index &= ~0x3; > > > + val = readl_relaxed(base + offset + index); > > > + val &= ~prio_offset_mask; > > > + val |= prio << prio_offset_shift; > > > + writel_relaxed(val, base + offset + index); > > > } > > > > > > static u32 gic_get_ppi_index(struct irq_data *d) > > > > From the architecture spec: > > > > > > 11.1.3 GIC memory-mapped register access > > > > In any system, access to the following registers must be supported: > > > > [...] > > * Byte accesses to: > > - GICD_IPRIORITYR. > > - GICD_ITARGETSR. > > - GICD_SPENDSGIR. > > - GICD_CPENDSGIR. > > - GICR_IPRIORITYR. > > > > > > So if GIC600 doesn't follow this architectural requirement, this is a > > HW erratum, and I want an actual description of the HW issue together > > with an erratum number. > > > > Lorenzo, can you please investigate on your side? > > Sure - I will look into it and report back. Checked - I don't think this patch is needed so it should be dropped and a follow-up discussion can continue in the relevant/appropriate forum - if there is anything left to discuss. Thanks, Lorenzo