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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id p12sm5278968pjo.4.2021.04.22.07.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 07:10:01 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: olof@lixom.net, arnd@kernel.org, w@1wt.eu, Daniel Palmer Subject: [RFC PATCH 2/2] ARM: mstar: Add header with macros for XIU register access Date: Thu, 22 Apr 2021 23:09:45 +0900 Message-Id: <20210422140945.4131092-3-daniel@0x0f.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210422140945.4131092-1-daniel@0x0f.com> References: <20210422140945.4131092-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Registers connected to the CPU via "XIU" (Maybe eXtended Interface Unit) are 32bits wide with a 64bit stride. Apparently someone realised that splitting 32bit registers into two 16bit ones was silly but at the same time didn't want to fix all of the register offsets used for "RIU" in their code. This means that any existing driver (i.e. the usb and ethernet) cannot be used as is and needs to use a special readl()/writel() to fix up the address of the register that needs to be accessed. To avoid having this code in every driver add a header with an implementation of readl()/writel() that patches over the insanity. Signed-off-by: Daniel Palmer --- include/soc/mstar/xiu.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 include/soc/mstar/xiu.h diff --git a/include/soc/mstar/xiu.h b/include/soc/mstar/xiu.h new file mode 100644 index 000000000000..d658338b8006 --- /dev/null +++ b/include/soc/mstar/xiu.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SOC_MSTAR_XIU_H_ +#define _SOC_MSTAR_XIU_H_ + +#include + +static inline u32 xiu_readl(__iomem void *base, unsigned int offset) +{ + __iomem void *reg = base + (offset * 2); + + return readl_relaxed(reg); +} + +static inline void xiu_writel(__iomem void *base, unsigned int offset, u32 value) +{ + __iomem void *reg = base + (offset * 2); + + writel_relaxed(value, reg); +} + +#endif -- 2.31.0