From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5982C43460 for ; Wed, 28 Apr 2021 19:38:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF45461151 for ; Wed, 28 Apr 2021 19:38:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241944AbhD1TjI (ORCPT ); Wed, 28 Apr 2021 15:39:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241844AbhD1Ti6 (ORCPT ); Wed, 28 Apr 2021 15:38:58 -0400 Received: from mail-qv1-xf4a.google.com (mail-qv1-xf4a.google.com [IPv6:2607:f8b0:4864:20::f4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73EC9C06138E for ; Wed, 28 Apr 2021 12:38:08 -0700 (PDT) Received: by mail-qv1-xf4a.google.com with SMTP id 99-20020a0c80ec0000b029017de514d56fso28892569qvb.17 for ; Wed, 28 Apr 2021 12:38:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Xmnri5WQ2+orpUoy8Yah+jBeLizzxPOC9TaH0yNsUEw=; b=oUpZGl/Vd2qkyf4SEL16T8TOpKEn5WhjXx4VgQpa0lSAh9RnrVFX6/2Imp5MadfmY5 1+VzIv5fC88MCSeyRjIc3T1M6SS80CR4qys0B6+MC5eN/YViCPyMVix1ipyDoh7zdOmu Vlz11OlwUpHnSBi5+7GZOOuBr259U6xnle8I/FXd43fuYu4zx+4RnttJHuhowMMMovMV +CH0346wj3qt9NQolRPCggW8BNYhgge1e8Cj4Gp7xS3KV1iZmbOQGYJVjWmYjnModCvc XpDbwO+U9EjhNfN3LadxEY92OYMKdG2BAZR/V//v94Ui5DdMLjRzwn8cBtY1VhPbhsOl 4mrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Xmnri5WQ2+orpUoy8Yah+jBeLizzxPOC9TaH0yNsUEw=; b=ogOOV3yhB/sYwHMlJWgFPbO5+/XwD2vfoAc5L7IFGC8OQDsk4/tad1Xa1ZUTTxyG72 jU3scOk6QxYgWixEjxSe/v259s+oMldA71lu/0EThSDazxTlhh1oQKBkJ+tS5B9dpz2x rmYnKDDgEbOoUaQAfU+PPa96esMnVNxw6kR1eU9V3y9CK7yr9w3AIwcJQTBQcmrF4lQN VQQ3jHvpKzt5/tbtcXOJkbuBPMCYeZx4ImPwXS52LJPb+/hcP29R5Or7A5G7j+6dNx3e heEgSXK4DA/5hDBpsVb0UOxf5da37AQfaVeeT538QcGZePpPAsCiDJxCnVP666Xem6mk R3mQ== X-Gm-Message-State: AOAM532d88uWYBDPHDbdzlOg1yhPdsel+vzULGWBG14mRsZGIb6huTrJ +AlnNmQP3Vq5SmSYytsYY0oYBnhfAYvXQw== X-Google-Smtp-Source: ABdhPJyHfYEnIMTt5sC77fB90YETDOON4FUQfvWdf6od6TH9hQ03ldd2gzkcG2ATyN/FvIqgivRA84an1WMgIw== X-Received: from ricarkol2.c.googlers.com ([fda3:e722:ac3:10:24:72f4:c0a8:62fe]) (user=ricarkol job=sendgmr) by 2002:a05:6214:258d:: with SMTP id fq13mr9099903qvb.50.1619638687593; Wed, 28 Apr 2021 12:38:07 -0700 (PDT) Date: Wed, 28 Apr 2021 12:37:53 -0700 In-Reply-To: <20210428193756.2110517-1-ricarkol@google.com> Message-Id: <20210428193756.2110517-4-ricarkol@google.com> Mime-Version: 1.0 References: <20210428193756.2110517-1-ricarkol@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [PATCH v2 3/6] x86/cpu: Expose CPUID regs, leaf and index definitions to tools From: Ricardo Koller To: Paolo Bonzini Cc: kvm@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , "H. Peter Anvin" , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Nathan Chancellor , Nick Desaulniers , linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com, Ricardo Koller Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move cpuid_regs, cpuid_regs_idx, and cpuid_leafs out of their '#ifdef __KERNEL__' guards so that KVM selftests can reuse the definitions in future patches. Move cpuid_regs and cpuid_regs_idx from processor.h to cpufeature.h to avoid blasting processor.h with several '#ifdefs'. Suggested-by: Sean Christopherson Signed-off-by: Ricardo Koller --- arch/x86/events/intel/pt.c | 1 + arch/x86/include/asm/cpufeature.h | 23 ++++++++++++++++++----- arch/x86/include/asm/processor.h | 11 ----------- arch/x86/kernel/cpu/scattered.c | 2 +- arch/x86/kernel/cpuid.c | 2 +- 5 files changed, 21 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index e94af4a54d0d..882b1478556e 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "../perf_event.h" #include "pt.h" diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 1728d4ce5730..22458ab5aac4 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -2,12 +2,19 @@ #ifndef _ASM_X86_CPUFEATURE_H #define _ASM_X86_CPUFEATURE_H -#include +#include -#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +#ifndef __ASSEMBLY__ +struct cpuid_regs { + u32 eax, ebx, ecx, edx; +}; -#include -#include +enum cpuid_regs_idx { + CPUID_EAX = 0, + CPUID_EBX, + CPUID_ECX, + CPUID_EDX, +}; enum cpuid_leafs { @@ -32,6 +39,11 @@ enum cpuid_leafs CPUID_7_EDX, CPUID_8000_001F_EAX, }; +#ifdef __KERNEL__ + +#include +#include +#include #ifdef CONFIG_X86_FEATURE_NAMES extern const char * const x86_cap_flags[NCAPINTS*32]; @@ -240,5 +252,6 @@ static __always_inline bool _static_cpu_has(u16 bit) #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ boot_cpu_data.x86_model -#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ +#endif /* defined(__KERNEL__) */ +#endif /* !defined(__ASSEMBLY__) */ #endif /* _ASM_X86_CPUFEATURE_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index f1b9ed5efaa9..1d355d2a6e4e 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -142,17 +142,6 @@ struct cpuinfo_x86 { unsigned initialized : 1; } __randomize_layout; -struct cpuid_regs { - u32 eax, ebx, ecx, edx; -}; - -enum cpuid_regs_idx { - CPUID_EAX = 0, - CPUID_EBX, - CPUID_ECX, - CPUID_EDX, -}; - #define X86_VENDOR_INTEL 0 #define X86_VENDOR_CYRIX 1 #define X86_VENDOR_AMD 2 diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 21d1f062895a..bcbcda1e329b 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include "cpu.h" diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index 6f7b8cc1bc9f..23e67220445b 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -37,7 +37,7 @@ #include #include -#include +#include #include static struct class *cpuid_class; -- 2.31.1.498.g6c1eba8ee3d-goog