From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: jassisinghbrar@gmail.com, robh+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
o.rempel@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com,
linux-imx@nxp.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support
Date: Fri, 7 May 2021 18:19:22 +0800 [thread overview]
Message-ID: <20210507101926.25631-1-peng.fan@oss.nxp.com> (raw)
From: Peng Fan <peng.fan@nxp.com>
i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
It has different register layout and bit position, but the register name
and bit definitions are almost same with previous i.MX MU.
So we extend the current imx-mailbox driver to support i.MX8ULP.
Peng Fan (4):
dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
mailbox: imx: replace the xTR/xRR array with single register
mailbox: imx: add xSR/xCR register array
mailbox: imx-mailbox: support i.MX8ULP MU
.../devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
drivers/mailbox/imx-mailbox.c | 196 +++++++++++-------
2 files changed, 123 insertions(+), 74 deletions(-)
--
2.30.0
next reply other threads:[~2021-05-07 9:47 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-07 10:19 Peng Fan (OSS) [this message]
2021-05-07 10:19 ` [PATCH 1/4] dt-bindings: mailbox: imx-mu: " Peng Fan (OSS)
2021-05-10 15:49 ` Rob Herring
2021-05-07 10:19 ` [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register Peng Fan (OSS)
2021-05-26 6:58 ` Daniel Baluta
2021-05-27 0:36 ` Peng Fan (OSS)
2021-05-07 10:19 ` [PATCH 3/4] mailbox: imx: add xSR/xCR register array Peng Fan (OSS)
2021-05-07 10:19 ` [PATCH 4/4] mailbox: imx-mailbox: support i.MX8ULP MU Peng Fan (OSS)
2021-05-26 6:06 ` [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support Peng Fan (OSS)
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