From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB895C433B4 for ; Thu, 13 May 2021 15:50:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 858B061354 for ; Thu, 13 May 2021 15:50:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234438AbhEMPvr (ORCPT ); Thu, 13 May 2021 11:51:47 -0400 Received: from mga12.intel.com ([192.55.52.136]:24114 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232345AbhEMPvM (ORCPT ); Thu, 13 May 2021 11:51:12 -0400 IronPort-SDR: Dm0ScYOBegcqKsQsa0BPE5Dz12cEI3xdT5DXzA0tN12fyn5otcsUjiiWadRmBzclr3nOmbnk4M rL48N35x8wQQ== X-IronPort-AV: E=McAfee;i="6200,9189,9982"; a="179568916" X-IronPort-AV: E=Sophos;i="5.82,296,1613462400"; d="scan'208";a="179568916" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 08:50:01 -0700 IronPort-SDR: 4WwB/5qQFGlYohLlqJtaRn1iNJub3aTNyMmeXcXdmJfhLFnocdLUpOrkMlmQPq08kTGqSnBEOe 3rokZkWgXeew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,296,1613462400"; d="scan'208";a="610418847" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga005.jf.intel.com with ESMTP; 13 May 2021 08:50:01 -0700 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Ingo Molnar , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Len Brown , Srinivas Pandruvada , Tim Chen , Aubrey Li , "Ravi V. Shankar" , Ricardo Neri , Quentin Perret , "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, Ricardo Neri , Aubrey Li , Daniel Bristot de Oliveira Subject: [PATCH v3 6/6] x86/sched: Enable SMT checks for asymmetric packing in load balancing Date: Thu, 13 May 2021 08:49:09 -0700 Message-Id: <20210513154909.6385-7-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210513154909.6385-1-ricardo.neri-calderon@linux.intel.com> References: <20210513154909.6385-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ITMT relies on asymmetric packing of tasks to ensure CPUs are populated in priority order. When balancing load, the scheduler compares scheduling groups in pairs, and compares only the priority of the CPUs of highest priority in the group. This may result on CPUs with medium priority being overlooked. A recent change introduced logic to also consider the idle state of the SMT siblings of the CPU doing the load balance. Enable those checks for x86 when using ITMT. Cc: Aubrey Li Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Mel Gorman Cc: Quentin Perret Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim Chen Reviewed-by: Len Brown Signed-off-by: Ricardo Neri --- Changes since v2: * Removed arch_sched_asym_prefer_early() as it is no longer needed. Changes since v1: * None --- arch/x86/kernel/itmt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 1afbdd1dd777..3c8f0cead574 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -28,6 +28,8 @@ DEFINE_PER_CPU_READ_MOSTLY(int, sched_core_priority); /* Boolean to track if system has ITMT capabilities */ static bool __read_mostly sched_itmt_capable; +/* Boolean to activate checks on the state of SMT siblings */ +static bool __read_mostly sched_itmt_smt_checks; /* * Boolean to control whether we want to move processes to cpu capable @@ -124,6 +126,8 @@ int sched_set_itmt_support(void) sysctl_sched_itmt_enabled = 1; + sched_itmt_smt_checks = true; + x86_topology_update = true; rebuild_sched_domains(); @@ -160,6 +164,7 @@ void sched_clear_itmt_support(void) if (sysctl_sched_itmt_enabled) { /* disable sched_itmt if we are no longer ITMT capable */ sysctl_sched_itmt_enabled = 0; + sched_itmt_smt_checks = false; x86_topology_update = true; rebuild_sched_domains(); } @@ -167,6 +172,11 @@ void sched_clear_itmt_support(void) mutex_unlock(&itmt_update_mutex); } +bool arch_asym_check_smt_siblings(void) +{ + return sched_itmt_smt_checks; +} + int arch_asym_cpu_priority(int cpu) { return per_cpu(sched_core_priority, cpu); -- 2.17.1