From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C004C433B4 for ; Wed, 19 May 2021 06:57:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD68D6135B for ; Wed, 19 May 2021 06:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235379AbhESG6Z (ORCPT ); Wed, 19 May 2021 02:58:25 -0400 Received: from verein.lst.de ([213.95.11.211]:36976 "EHLO verein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232019AbhESG6V (ORCPT ); Wed, 19 May 2021 02:58:21 -0400 Received: by verein.lst.de (Postfix, from userid 2407) id ADB9468B05; Wed, 19 May 2021 08:56:58 +0200 (CEST) Date: Wed, 19 May 2021 08:56:58 +0200 From: Christoph Hellwig To: Drew Fustini Cc: Christoph Hellwig , Guo Ren , Anup Patel , Palmer Dabbelt , wefu@redhat.com, lazyparser@gmail.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , paul.walmsley@sifive.com Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Message-ID: <20210519065658.GB31590@lst.de> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519060617.GA28397@lst.de> <20210519065431.GB3076809@x1> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210519065431.GB3076809@x1> User-Agent: Mutt/1.5.17 (2007-11-01) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 18, 2021 at 11:54:31PM -0700, Drew Fustini wrote: > Isn't it a good goal for Linux to support the capabilities present in > the SoC that a currently being fab'd? > > I believe the CMO group only started last year [1] so the RV64GC SoCs > that are going into mass production this year would not have had the > opporuntiy of utilizing any RISC-V ISA extension for handling cache > management. Then the vendors need to push harder. This problem has been known for years but ignored by the vendors.