Hi Rodrigo, FYI, the error/warning still remains. tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 625acffd7ae2c52898d249e6c5c39f348db0d8df commit: 688f97ed3f5e339c0c2c09d9ee7ff23d5807b0a7 drm/amd/display: Add vupdate_no_lock interrupts for DCN2.1 date: 4 months ago config: i386-randconfig-r024-20210627 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=688f97ed3f5e339c0c2c09d9ee7ff23d5807b0a7 git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout 688f97ed3f5e339c0c2c09d9ee7ff23d5807b0a7 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:43:20: warning: no previous prototype for 'to_dal_irq_source_dcn21' [-Wmissing-prototypes] 43 | enum dc_irq_source to_dal_irq_source_dcn21( | ^~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init] 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[72]') 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | >> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init] 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[73]') 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | >> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init] 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[74]') 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | >> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init] 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[75]') 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | >> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init] 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[76]') 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | >> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init] 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[77]') 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry' 242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ | ^~ 243 | IRQ_REG_ENTRY(OTG, reg_num,\ | vim +242 drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c 42 > 43 enum dc_irq_source to_dal_irq_source_dcn21( 44 struct irq_service *irq_service, 45 uint32_t src_id, 46 uint32_t ext_id) 47 { 48 switch (src_id) { 49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 50 return DC_IRQ_SOURCE_VBLANK1; 51 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 52 return DC_IRQ_SOURCE_VBLANK2; 53 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 54 return DC_IRQ_SOURCE_VBLANK3; 55 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 56 return DC_IRQ_SOURCE_VBLANK4; 57 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 58 return DC_IRQ_SOURCE_VBLANK5; 59 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 60 return DC_IRQ_SOURCE_VBLANK6; 61 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 62 return DC_IRQ_SOURCE_PFLIP1; 63 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 64 return DC_IRQ_SOURCE_PFLIP2; 65 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 66 return DC_IRQ_SOURCE_PFLIP3; 67 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 68 return DC_IRQ_SOURCE_PFLIP4; 69 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 70 return DC_IRQ_SOURCE_PFLIP5; 71 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 72 return DC_IRQ_SOURCE_PFLIP6; 73 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 74 return DC_IRQ_SOURCE_VUPDATE1; 75 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 76 return DC_IRQ_SOURCE_VUPDATE2; 77 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 78 return DC_IRQ_SOURCE_VUPDATE3; 79 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 80 return DC_IRQ_SOURCE_VUPDATE4; 81 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 82 return DC_IRQ_SOURCE_VUPDATE5; 83 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 84 return DC_IRQ_SOURCE_VUPDATE6; 85 86 case DCN_1_0__SRCID__DC_HPD1_INT: 87 /* generic src_id for all HPD and HPDRX interrupts */ 88 switch (ext_id) { 89 case DCN_1_0__CTXID__DC_HPD1_INT: 90 return DC_IRQ_SOURCE_HPD1; 91 case DCN_1_0__CTXID__DC_HPD2_INT: 92 return DC_IRQ_SOURCE_HPD2; 93 case DCN_1_0__CTXID__DC_HPD3_INT: 94 return DC_IRQ_SOURCE_HPD3; 95 case DCN_1_0__CTXID__DC_HPD4_INT: 96 return DC_IRQ_SOURCE_HPD4; 97 case DCN_1_0__CTXID__DC_HPD5_INT: 98 return DC_IRQ_SOURCE_HPD5; 99 case DCN_1_0__CTXID__DC_HPD6_INT: 100 return DC_IRQ_SOURCE_HPD6; 101 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 102 return DC_IRQ_SOURCE_HPD1RX; 103 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 104 return DC_IRQ_SOURCE_HPD2RX; 105 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 106 return DC_IRQ_SOURCE_HPD3RX; 107 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 108 return DC_IRQ_SOURCE_HPD4RX; 109 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 110 return DC_IRQ_SOURCE_HPD5RX; 111 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 112 return DC_IRQ_SOURCE_HPD6RX; 113 default: 114 return DC_IRQ_SOURCE_INVALID; 115 } 116 break; 117 118 default: 119 break; 120 } 121 return DC_IRQ_SOURCE_INVALID; 122 } 123 124 static bool hpd_ack( 125 struct irq_service *irq_service, 126 const struct irq_source_info *info) 127 { 128 uint32_t addr = info->status_reg; 129 uint32_t value = dm_read_reg(irq_service->ctx, addr); 130 uint32_t current_status = 131 get_reg_field_value( 132 value, 133 HPD0_DC_HPD_INT_STATUS, 134 DC_HPD_SENSE_DELAYED); 135 136 dal_irq_service_ack_generic(irq_service, info); 137 138 value = dm_read_reg(irq_service->ctx, info->enable_reg); 139 140 set_reg_field_value( 141 value, 142 current_status ? 0 : 1, 143 HPD0_DC_HPD_INT_CONTROL, 144 DC_HPD_INT_POLARITY); 145 146 dm_write_reg(irq_service->ctx, info->enable_reg, value); 147 148 return true; 149 } 150 151 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 152 .set = NULL, 153 .ack = hpd_ack 154 }; 155 156 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 157 .set = NULL, 158 .ack = NULL 159 }; 160 161 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 162 .set = NULL, 163 .ack = NULL 164 }; 165 166 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 167 .set = NULL, 168 .ack = NULL 169 }; 170 171 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 172 .set = NULL, 173 .ack = NULL 174 }; 175 176 #undef BASE_INNER 177 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 178 179 /* compile time expand base address. */ 180 #define BASE(seg) \ 181 BASE_INNER(seg) 182 183 184 #define SRI(reg_name, block, id)\ 185 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 186 mm ## block ## id ## _ ## reg_name 187 188 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 190 .enable_reg = SRI(reg1, block, reg_num),\ 191 .enable_mask = \ 192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 193 .enable_value = {\ 194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 196 },\ 197 .ack_reg = SRI(reg2, block, reg_num),\ 198 .ack_mask = \ 199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 200 .ack_value = \ 201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 202 203 204 205 #define hpd_int_entry(reg_num)\ 206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 207 IRQ_REG_ENTRY(HPD, reg_num,\ 208 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 209 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 211 .funcs = &hpd_irq_info_funcs\ 212 } 213 214 #define hpd_rx_int_entry(reg_num)\ 215 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 216 IRQ_REG_ENTRY(HPD, reg_num,\ 217 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 218 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 220 .funcs = &hpd_rx_irq_info_funcs\ 221 } 222 #define pflip_int_entry(reg_num)\ 223 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 224 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 225 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 226 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 227 .funcs = &pflip_irq_info_funcs\ 228 } 229 230 #define vupdate_int_entry(reg_num)\ 231 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 232 IRQ_REG_ENTRY(OTG, reg_num,\ 233 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\ 234 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\ 235 .funcs = &vblank_irq_info_funcs\ 236 } 237 238 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 239 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 240 */ 241 #define vupdate_no_lock_int_entry(reg_num)\ > 242 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 243 IRQ_REG_ENTRY(OTG, reg_num,\ 244 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 245 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 246 .funcs = &vupdate_no_lock_irq_info_funcs\ 247 } 248 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org