From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8C62C11F82 for ; Tue, 6 Jul 2021 11:44:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C299461E50 for ; Tue, 6 Jul 2021 11:44:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240106AbhGFLqH (ORCPT ); Tue, 6 Jul 2021 07:46:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:42590 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235089AbhGFLd4 (ORCPT ); Tue, 6 Jul 2021 07:33:56 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9201161D2F; Tue, 6 Jul 2021 11:23:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625570587; bh=G2nzf0gXd2W5OSMmOy62iXfCIWuNGIizdeqqd4gYbWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jPPLotg2hAi1hTdVWolIRcjqLLrAXq1iuOD3LHq9vfzdN2DYBtCn4vL+20hyz2asU 1EJ7XRKmxzPvs4Mx7W+koldOYN3Wy70YS3q7cTSBFs++Yz/XyjWhniqzgerjDIN0gW zlEEaK7F7Mgbd5/DtS+MBPFFHFRHbbXqYOlbIyEKEqsM/PwwS07BwR/BIxkAIez8oH XhuJYBlK37ddAwuqPZ+SAARe9Wh5Q8qwA3zkx2lLwFLFikJCG/k7PqhYD120/X9Rsm QHPRX6URD3xGBWyUn1sD/KChONCuqPxE9iS4xd2+T6SuEU8OrPk1LA55jGpGxJSEnI ur85vzlF4KMmQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Paul Cercueil , Thomas Bogendoerfer , Sasha Levin , linux-mips@vger.kernel.org Subject: [PATCH AUTOSEL 5.10 049/137] MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER Date: Tue, 6 Jul 2021 07:20:35 -0400 Message-Id: <20210706112203.2062605-49-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210706112203.2062605-1-sashal@kernel.org> References: <20210706112203.2062605-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Paul Cercueil [ Upstream commit eb3849370ae32b571e1f9a63ba52c61adeaf88f7 ] The clock driving the XBurst CPUs in Ingenic SoCs is integer divided from the main PLL. As such, it is possible to control the frequency of the CPU, either by changing the divider, or by changing the rate of the main PLL. The XBurst CPUs also lack the CP0 timer; the TCU, a separate piece of hardware in the SoC, provides this functionality. Signed-off-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1917ccd39256..1a63f592034e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -418,6 +418,8 @@ config MACH_INGENIC_SOC select MIPS_GENERIC select MACH_INGENIC select SYS_SUPPORTS_ZBOOT_UART16550 + select CPU_SUPPORTS_CPUFREQ + select MIPS_EXTERNAL_TIMER config LANTIQ bool "Lantiq based platforms" -- 2.30.2