From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05964C4338F for ; Sat, 7 Aug 2021 14:55:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D16FD610A6 for ; Sat, 7 Aug 2021 14:55:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230002AbhHGO4B (ORCPT ); Sat, 7 Aug 2021 10:56:01 -0400 Received: from out4436.biz.mail.alibaba.com ([47.88.44.36]:43167 "EHLO out4436.biz.mail.alibaba.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbhHGOz7 (ORCPT ); Sat, 7 Aug 2021 10:55:59 -0400 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R231e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=alimailimapcm10staff010182156082;MF=xianting.tian@linux.alibaba.com;NM=1;PH=DS;RN=6;SR=0;TI=SMTPD_---0UiE-sLH_1628348139; Received: from localhost(mailfrom:xianting.tian@linux.alibaba.com fp:SMTPD_---0UiE-sLH_1628348139) by smtp.aliyun-inc.com(127.0.0.1); Sat, 07 Aug 2021 22:55:39 +0800 From: Xianting Tian To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xianting Tian Subject: [PATCH] riscv: add ARCH_DMA_MINALIGN support Date: Sat, 7 Aug 2021 22:55:37 +0800 Message-Id: <20210807145537.124744-1-xianting.tian@linux.alibaba.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce ARCH_DMA_MINALIGN to riscv arch. Signed-off-by: Xianting Tian --- arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b1045..2945bbe2b 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -11,6 +11,8 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + /* * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that * the flat loader aligns it accordingly. -- 2.17.1