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Peter Anvin" , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Michael Petlan , "Frank Ch. Eigler" , Song Liu , x86@kernel.org, Daniel =?iso-8859-1?Q?D=EDaz?= , Andrii Nakryiko , Alexei Starovoitov , Sedat Dilek , Andi Kleen , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org Subject: Re: [PATCH v5 4/9] perf/x86: Add compiler barrier after updating BTS Message-ID: <20210829105657.GC14461@leoy-ThinkPad-X240s> References: <20210809111407.596077-1-leo.yan@linaro.org> <20210809111407.596077-5-leo.yan@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210809111407.596077-5-leo.yan@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, or any x86 maintainer, On Mon, Aug 09, 2021 at 07:14:02PM +0800, Leo Yan wrote: > Since BTS is coherent, simply add a compiler barrier to separate the BTS > update and aux_head store. Could you reivew this patch and check if BTS needs the comipler barrier in this case? Thanks. > Signed-off-by: Leo Yan > --- > arch/x86/events/intel/bts.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c > index 6320d2cfd9d3..974e917e65b2 100644 > --- a/arch/x86/events/intel/bts.c > +++ b/arch/x86/events/intel/bts.c > @@ -209,6 +209,12 @@ static void bts_update(struct bts_ctx *bts) > } else { > local_set(&buf->data_size, head); > } > + > + /* > + * Since BTS is coherent, just add compiler barrier to ensure > + * BTS updating is ordered against bts::handle::event. > + */ > + barrier(); > } > > static int > -- > 2.25.1 >