From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F303C433F5 for ; Thu, 16 Sep 2021 13:00:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E78A760F3A for ; Thu, 16 Sep 2021 13:00:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239813AbhIPNBk (ORCPT ); Thu, 16 Sep 2021 09:01:40 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:9886 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239741AbhIPNBi (ORCPT ); Thu, 16 Sep 2021 09:01:38 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4H9HBX3jRxz8yXQ; Thu, 16 Sep 2021 20:55:48 +0800 (CST) Received: from dggema756-chm.china.huawei.com (10.1.198.198) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.8; Thu, 16 Sep 2021 21:00:15 +0800 Received: from localhost.localdomain (10.175.112.125) by dggema756-chm.china.huawei.com (10.1.198.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.8; Thu, 16 Sep 2021 21:00:15 +0800 From: Chen Huang To: Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Chen Huang , Kefeng Wang , Darius Rad , Jisheng Zhang , , Subject: [PATCH v2 0/2] riscv: improve unaligned memory accesses Date: Thu, 16 Sep 2021 13:08:53 +0000 Message-ID: <20210916130855.4054926-1-chenhuang5@huawei.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.175.112.125] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggema756-chm.china.huawei.com (10.1.198.198) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The patchset improves RISCV unaligned memory accesses, selects HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not enabled and supports DCACHE_WORD_ACCESS to improve the efficiency of unaligned memory accesses. If CPU don't support unaligned memory accesses for now, please select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU don't support unaligned memory accesses, I don't choose the CONFIG for them. Changes since v1: - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support unaligned memory accesses, add an option for CPUs to choose it or not. Chen Huang (2): riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS riscv: Support DCACHE_WORD_ACCESS arch/riscv/Kconfig | 5 ++++ arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.25.1