From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B67CC433FE for ; Sun, 10 Oct 2021 04:44:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 289FA60EFE for ; Sun, 10 Oct 2021 04:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229910AbhJJEqe (ORCPT ); Sun, 10 Oct 2021 00:46:34 -0400 Received: from mga02.intel.com ([134.134.136.20]:7333 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229694AbhJJEqc (ORCPT ); Sun, 10 Oct 2021 00:46:32 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10132"; a="213852610" X-IronPort-AV: E=Sophos;i="5.85,361,1624345200"; d="scan'208";a="213852610" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2021 21:44:34 -0700 X-IronPort-AV: E=Sophos;i="5.85,361,1624345200"; d="scan'208";a="489989569" Received: from iweiny-desk2.sc.intel.com (HELO localhost) ([10.3.52.147]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2021 21:44:34 -0700 Date: Sat, 9 Oct 2021 21:44:34 -0700 From: Ira Weiny To: Dan Williams Cc: linux-cxl@vger.kernel.org, Ben Widawsky , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Subject: Re: [PATCH v3 07/10] cxl/pci: Split cxl_pci_setup_regs() Message-ID: <20211010044434.GK3114988@iweiny-DESK2.sc.intel.com> References: <163379783658.692348.16064992154261275220.stgit@dwillia2-desk3.amr.corp.intel.com> <163379787433.692348.2451270397309803556.stgit@dwillia2-desk3.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <163379787433.692348.2451270397309803556.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: Mutt/1.11.1 (2018-12-01) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Oct 09, 2021 at 09:44:34AM -0700, Dan Williams wrote: > From: Ben Widawsky > > In preparation for moving parts of register mapping to cxl_core, split > cxl_pci_setup_regs() into a helper that finds register blocks, > (cxl_find_regblock()), and a generic wrapper that probes the precise > register sets within a block (cxl_setup_regs()). > > Move the actual mapping (cxl_map_regs()) of the only register-set that > cxl_pci cares about (memory device registers) up a level from the former > cxl_pci_setup_regs() into cxl_pci_probe(). > > With this change the unused component registers are no longer mapped, > but the helpers are primed to move into the core. > > Signed-off-by: Ben Widawsky > [djbw: rebase on the cxl_register_map refactor] > [djbw: drop cxl_map_regs() for component registers] Reviewed-by: Ira Weiny > Signed-off-by: Dan Williams > --- > drivers/cxl/pci.c | 73 +++++++++++++++++++++++++++-------------------------- > 1 file changed, 37 insertions(+), 36 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index b42407d067ac..b6bc8e5ca028 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -433,72 +433,69 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi, > } > > /** > - * cxl_pci_setup_regs() - Setup necessary MMIO. > - * @cxlm: The CXL memory device to communicate with. > + * cxl_find_regblock() - Locate register blocks by type > + * @pdev: The CXL PCI device to enumerate. > + * @type: Register Block Indicator id > + * @map: Enumeration output, clobbered on error > * > - * Return: 0 if all necessary registers mapped. > + * Return: 0 if register block enumerated, negative error code otherwise > * > - * A memory device is required by spec to implement a certain set of MMIO > - * regions. The purpose of this function is to enumerate and map those > - * registers. > + * A CXL DVSEC may additional point one or more register blocks, search > + * for them by @type. > */ > -static int cxl_pci_setup_regs(struct cxl_mem *cxlm) > +static int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, > + struct cxl_register_map *map) > { > u32 regloc_size, regblocks; > - int regloc, i, n_maps, ret = 0; > - struct device *dev = cxlm->dev; > - struct pci_dev *pdev = to_pci_dev(dev); > - struct cxl_register_map *map, maps[CXL_REGLOC_RBI_TYPES]; > + int regloc, i; > > regloc = cxl_pci_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID); > - if (!regloc) { > - dev_err(dev, "register location dvsec not found\n"); > + if (!regloc) > return -ENXIO; > - } > > - /* Get the size of the Register Locator DVSEC */ > pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); > regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); > > regloc += PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET; > regblocks = (regloc_size - PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET) / 8; > > - for (i = 0, n_maps = 0; i < regblocks; i++, regloc += 8) { > + for (i = 0; i < regblocks; i++, regloc += 8) { > u32 reg_lo, reg_hi; > > pci_read_config_dword(pdev, regloc, ®_lo); > pci_read_config_dword(pdev, regloc + 4, ®_hi); > > - map = &maps[n_maps]; > cxl_decode_regblock(reg_lo, reg_hi, map); > > - /* Ignore unknown register block types */ > - if (map->reg_type > CXL_REGLOC_RBI_MEMDEV) > - continue; > + if (map->reg_type == type) > + return 0; > + } > > - ret = cxl_map_regblock(pdev, map); > - if (ret) > - return ret; > + return -ENODEV; > +} > > - ret = cxl_probe_regs(pdev, map); > - cxl_unmap_regblock(pdev, map); > - if (ret) > - return ret; > +static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > + struct cxl_register_map *map) > +{ > + int rc; > > - n_maps++; > - } > + rc = cxl_find_regblock(pdev, type, map); > + if (rc) > + return rc; > > - for (i = 0; i < n_maps; i++) { > - ret = cxl_map_regs(cxlm, &maps[i]); > - if (ret) > - break; > - } > + rc = cxl_map_regblock(pdev, map); > + if (rc) > + return rc; > + > + rc = cxl_probe_regs(pdev, map); > + cxl_unmap_regblock(pdev, map); > > - return ret; > + return rc; > } > > static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > + struct cxl_register_map map; > struct cxl_memdev *cxlmd; > struct cxl_mem *cxlm; > int rc; > @@ -518,7 +515,11 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > if (IS_ERR(cxlm)) > return PTR_ERR(cxlm); > > - rc = cxl_pci_setup_regs(cxlm); > + rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); > + if (rc) > + return rc; > + > + rc = cxl_map_regs(cxlm, &map); > if (rc) > return rc; > >