From: Flora Fu <flora.fu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Mark Brown <broonie@kernel.org>,
Sumit Semwal <sumit.semwal@linaro.org>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-media@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
<linaro-mm-sig@lists.linaro.org>,
Flora Fu <flora.fu@mediatek.com>, Yong Wu <yong.wu@mediatek.com>,
Pi-Cheng Chen <pi-cheng.chen@mediatek.com>
Subject: [RFC 11/13] arm64: dts: mt8192: Add apu power nodes
Date: Sat, 23 Oct 2021 19:14:07 +0800 [thread overview]
Message-ID: <20211023111409.30463-12-flora.fu@mediatek.com> (raw)
In-Reply-To: <20211023111409.30463-1-flora.fu@mediatek.com>
Add apu power node.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 62 ++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d5e417a512a7..c505c6926839 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -964,6 +964,68 @@
};
};
+ apusys_power: apusys_power@190f1000 {
+ compatible = "mediatek,apusys-power",
+ "mediatek,mt8192-apu-power";
+ reg = <0 0x190f1000 0 0x1000>,
+ <0 0x19000600 0 0x100>;
+ reg-names = "apu_pcu",
+ "apu_spare";
+ power-domains = <&apuspm 0>;
+ clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_DSP1_SEL>,
+ <&topckgen CLK_TOP_DSP1_NPUPLL_SEL>,
+ <&topckgen CLK_TOP_DSP2_SEL>,
+ <&topckgen CLK_TOP_DSP2_NPUPLL_SEL>,
+ <&topckgen CLK_TOP_DSP5_SEL>,
+ <&topckgen CLK_TOP_DSP5_APUPLL_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D2>,
+ <&topckgen CLK_TOP_UNIVPLL_D4_D2>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_MMPLL_D6>,
+ <&topckgen CLK_TOP_MMPLL_D5>,
+ <&topckgen CLK_TOP_MMPLL_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5>,
+ <&topckgen CLK_TOP_UNIVPLL_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D3>,
+ <&topckgen CLK_TOP_MAINPLL_D6>,
+ <&topckgen CLK_TOP_MAINPLL_D4>,
+ <&topckgen CLK_TOP_MAINPLL_D3>,
+ <&topckgen CLK_TOP_TVDPLL>,
+ <&topckgen CLK_TOP_APUPLL>,
+ <&topckgen CLK_TOP_NPUPLL>,
+ <&apmixedsys CLK_APMIXED_APUPLL>,
+ <&apmixedsys CLK_APMIXED_NPUPLL>;
+ clock-names = "clk_top_dsp_sel",
+ "clk_top_dsp1_sel",
+ "clk_top_dsp1_npupll_sel",
+ "clk_top_dsp2_sel",
+ "clk_top_dsp2_npupll_sel",
+ "clk_top_dsp5_sel",
+ "clk_top_dsp5_apupll_sel",
+ "clk_top_ipu_if_sel",
+ "clk_top_clk26m",
+ "clk_top_mainpll_d4_d2",
+ "clk_top_univpll_d4_d2",
+ "clk_top_univpll_d6_d2",
+ "clk_top_mmpll_d6",
+ "clk_top_mmpll_d5",
+ "clk_top_mmpll_d4",
+ "clk_top_univpll_d5",
+ "clk_top_univpll_d4",
+ "clk_top_univpll_d3",
+ "clk_top_mainpll_d6",
+ "clk_top_mainpll_d4",
+ "clk_top_mainpll_d3",
+ "clk_top_tvdpll_ck",
+ "clk_top_apupll_ck",
+ "clk_top_npupll_ck",
+ "clk_apmixed_apupll_rate",
+ "clk_apmixed_npupll_rate";
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
--
2.18.0
next prev parent reply other threads:[~2021-10-23 11:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-23 11:13 [RFC 00/13] MediaTek MT8192 APU Flora Fu
2021-10-23 11:13 ` [RFC 01/13] dt-bindings: soc: mediatek: apusys: add mt8192 apu iommu bindings Flora Fu
2021-10-23 11:13 ` [RFC 02/13] dt-bindings: soc: mediatek: apusys: Add new document for APU power Flora Fu
2021-10-23 11:13 ` [RFC 03/13] dt-bindings: soc: mediatek: apusys: Add new document for APU tinysys Flora Fu
2021-10-23 11:14 ` [RFC 04/13] iommu/mediatek: Add APU iommu support Flora Fu
2021-10-26 15:17 ` AngeloGioacchino Del Regno
2021-10-23 11:14 ` [RFC 05/13] soc: mediatek: Add command for APU SMC call Flora Fu
2021-10-23 11:14 ` [RFC 06/13] soc: mediatek: apu: Add apu core driver Flora Fu
2021-10-23 15:49 ` Randy Dunlap
2021-10-26 15:17 ` AngeloGioacchino Del Regno
2021-10-23 11:14 ` [RFC 07/13] soc: mediatek: apu: Add apu power driver Flora Fu
2021-10-23 11:14 ` [RFC 08/13] soc: mediatek: apu: Add apusys rv driver Flora Fu
2021-10-26 15:21 ` AngeloGioacchino Del Regno
[not found] ` <0248142e6e0b55fe12f179e74b77375b386082ee.camel@mediatek.com>
2021-11-26 10:07 ` AngeloGioacchino Del Regno
2021-10-23 11:14 ` [RFC 09/13] soc: mediatek: apu: Add middleware driver Flora Fu
2021-10-23 11:14 ` [RFC 10/13] arm64: dts: mt8192: Add APU-IOMMU nodes Flora Fu
2021-10-23 11:14 ` Flora Fu [this message]
2021-10-23 11:14 ` [RFC 12/13] arm64: dts: mt8192: Add apu tinysys Flora Fu
2021-10-26 15:18 ` AngeloGioacchino Del Regno
2021-10-23 11:14 ` [RFC 13/13] arm64: dts: mt8192: Add regulator for APU Flora Fu
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