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Tue, 26 Oct 2021 12:31:52 +0000 From: Prathamesh Shete To: , , , , , CC: , , Subject: [PATCH] pinctrl: tegra: Fix warnings and error Date: Tue, 26 Oct 2021 18:01:48 +0530 Message-ID: <20211026123148.14500-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 10039344-6c5f-4901-cf98-08d9987c9894 X-MS-TrafficTypeDiagnostic: CY4PR12MB1800: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:121; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CbhKbayV3JVkJhV/o8rCFLf3EyjU3rUs/41x10HjAq2Xwe359n7VBxGQbcQbtd43sehMoUulbXilviK9tpU/lOpK6spKpkqbc1YrrFPsMTe9huQqZUw2Byn9PBKaydiJrSOOIYPgGQ9BOoWgO3vNbwRHmylHiQgONKXuoJXGdYg4zV64aDD5JHTPvQQqe11tD5+k0CVGlAkUQMByeS3LMnnvvFzTZ/Wo1WYJ9sxjMcK2/wrWdxzDKoBfOYMbn/lWOX1Xnk5Kff44Q4whzDoZ5CwJx1gNCeDUenSbsvX3vzCPEffxCOEwQx70eCmSrPBi91Jf9v9BPGKEPddfE9qOiD6RR5w2gzkwYESRCCp36z9bfgrZbzwrVtRwVn0vx+W47xPF+xt0oxaobLzYbU8tr4uvrP1ndMNl9olb8iDWvYBCtVWjtZjOka5DGh9jLd9MZR9oOdrxPO1P3uRIx1gwWoB0DCdP8W/Rnx1lPH+mpXTRitkCstgqo/L7H2SkeZGL2JaSXaJrVsxbIrlWEHccjjGOETX+LLkrvqRR7gaHGiZ6tKxlbbtpNELekq+xYesffdYzdlfMC6ZHikoOEwB7scGCAvToxu/KsBlMHXNkK4iPntT0pbBIh+B/Ha9OjYH4BWkSD7uQLAZ8TyzTjL3ADylwMZdte7V9HTIEZymSIa1f5BN7ByJmkLtRDxbZ5CFKC2xhppVHRHiOAARjT+cPMA== X-Forefront-Antispam-Report: CIP:216.228.112.32;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(5660300002)(110136005)(107886003)(186003)(70586007)(4326008)(7696005)(86362001)(426003)(2616005)(508600001)(47076005)(82310400003)(70206006)(1076003)(36756003)(7636003)(26005)(6666004)(8936002)(54906003)(83380400001)(336012)(356005)(316002)(36860700001)(8676002)(2906002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2021 12:31:55.0972 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10039344-6c5f-4901-cf98-08d9987c9894 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1800 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix warnings are errors caused by commit a42c7d95d29e ("pinctrl: tegra: Use correct offset for pin group"). Signed-off-by: Prathamesh Shete --- drivers/pinctrl/tegra/pinctrl-tegra.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 0471d9c7f0ba..8d734bfc33d2 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -279,7 +279,6 @@ static struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctlde unsigned int offset) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct tegra_pingroup *g; unsigned int group, num_pins, j; const unsigned int *pins; int ret; @@ -290,7 +289,7 @@ static struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctlde continue; for (j = 0; j < num_pins; j++) { if (offset == pins[j]) - return &pmx->soc->groups[group]; + return (struct tegra_pingroup *)&pmx->soc->groups[group]; } } @@ -338,7 +337,7 @@ static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, group = tegra_pinctrl_get_group(pctldev, offset); if (!group) - return -EINVAL; + return; if (group->mux_reg < 0 || group->sfsel_bit < 0) return; -- 2.17.1