From: Adam Ford <aford173@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: tharvey@gateworks.com, aford@beaconembedded.com,
Adam Ford <aford173@gmail.com>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>, Peng Fan <peng.fan@nxp.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH] soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active
Date: Sat, 20 Nov 2021 13:39:16 -0600 [thread overview]
Message-ID: <20211120193916.1309236-1-aford173@gmail.com> (raw)
Enable the vpu-h1 clock when the domain is active because reading
or writing to the VPU-H1 IP block cause the system to hang.
Fixes: 656ade7aa42a ("soc: imx: gpcv2: keep i.MX8M* bus clocks enabled")
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index b8d52d8d29db..7b6dfa33dcb9 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -734,6 +734,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
.map = IMX8MM_VPUH1_A53_DOMAIN,
},
.pgc = BIT(IMX8MM_PGC_VPUH1),
+ .keep_clocks = true,
},
[IMX8MM_POWER_DOMAIN_DISPMIX] = {
--
2.32.0
next reply other threads:[~2021-11-20 19:39 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 19:39 Adam Ford [this message]
2021-11-20 20:52 ` Fabio Estevam
2021-11-23 12:20 ` Shawn Guo
2022-03-31 9:28 ` Lucas Stach
2022-03-31 11:32 ` Adam Ford
2022-04-05 6:44 ` Shawn Guo
2022-04-05 9:55 ` Adam Ford
2022-04-05 10:07 ` Lucas Stach
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