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Sun, 12 Dec 2021 12:07:04 -0600 From: Ajit Kumar Pandey To: , CC: , , , , , Ajit Kumar Pandey , Michael Turquette , open list Subject: [PATCH v5 5/5] clk: x86: Fix clk_gate_flags for RV_CLK_GATE Date: Sun, 12 Dec 2021 23:35:27 +0530 Message-ID: <20211212180527.1641362-6-AjitKumar.Pandey@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211212180527.1641362-1-AjitKumar.Pandey@amd.com> References: <20211212180527.1641362-1-AjitKumar.Pandey@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2fd33008-fce7-4566-2fa9-08d9bd9a3658 X-MS-TrafficTypeDiagnostic: SN1PR12MB2431:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ihIxXNs+DqlPjYp1b7rgPZieswJsLZQ1Gz0tZwyGTX7wFvRjGc2/0VVdOh/jLDGnQIMzpaYl2PjxE9VAQ3Y5GeSyUU9o5re0SPz0D5vw1QbigODVoWeJNgqhKi+FmGeLDVoYOysLcM+RFlJqE14Amy+NlXONdg1KZL5IndLxte5BgadZfXp+Q2G6CKDQvPbLFWmZ5ksgRUockF1/hvZ/TIsQyuda5TdZ/CgY4j9s3YWW41bpIUSDtiWPzNYKVo6kbi3NAgt6snB/d6VAyXGKMpnxpo6h0vDHEXQjxZTiGiG3Jl1+L9AR5pHVI9rnyaCRlica/zEBDMh2L+Kpwo1c7CkmOyR5wv76SLdvH4bXqYCIsKZWs695r0uAPcGuSt+kTgNCGkT6D5ZjIh+boZ3AVujcByPJzy8t0GFLMZMUDmO6pQbWdwXmtOyB+1+ZAcwecEz4Qnk697PbcVJYfZStDqLEB99tqmpjmVHgRJhf6qn26br3Eif64KYmftCyd5HkaovY7bqt+1Y/AeWIvA/cuxnQ5NM0VaX2X7qay1wFy7uGQ2OBmNsrLEExsPxCKcFwEspUtaQJB0p2y+a8Ervv+JcDye0Nni1H7rRxXugOG3I9sZYvY39q0/m9h85YHRdBGG3G4KyYU7EsRx02MM3Osogp8tHbuX636etdAI7HICBSEWhwH3RuzZWsnPPC1jjJxYDF3N9wRilvQSYfv26ghYTc18gf3ZDlT31q09SHe5a+CJL2YgTFNhkgmE6JPOwhxSVL3pzEGOZZ5tK/+NGzK0dDTYP3712idPG4RlGSuXM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(81166007)(2906002)(82310400004)(316002)(356005)(86362001)(8936002)(110136005)(8676002)(1076003)(426003)(47076005)(36756003)(54906003)(36860700001)(40460700001)(6666004)(83380400001)(4744005)(70206006)(186003)(70586007)(5660300002)(336012)(7696005)(508600001)(4326008)(2616005)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2021 18:07:08.3216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fd33008-fce7-4566-2fa9-08d9bd9a3658 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2431 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In newer SoC we have to clear bit for disabling 48MHz oscillator clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable and disable of 48MHz clock. Signed-off-by: Ajit Kumar Pandey Reviewed-by: Mario Limonciello --- drivers/clk/x86/clk-fch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c index d41d519b9c2b..fdc060e75839 100644 --- a/drivers/clk/x86/clk-fch.c +++ b/drivers/clk/x86/clk-fch.c @@ -82,7 +82,7 @@ static int fch_clk_probe(struct platform_device *pdev) hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1", "clk48MHz", 0, fch_data->base + MISCCLKCNTL1, - OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL); + OSCCLKENB, 0, NULL); devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED], fch_data->name, NULL); -- 2.25.1