From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CBD5C433F5 for ; Fri, 17 Dec 2021 13:41:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232744AbhLQNl6 (ORCPT ); Fri, 17 Dec 2021 08:41:58 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:16965 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236689AbhLQNlz (ORCPT ); Fri, 17 Dec 2021 08:41:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639748515; x=1671284515; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=xX5ZSrbiNjNxR+hTc05BTwezwHcOHWTy1Olt7ni3p1k=; b=loL7EKdCHHucm4XkDQq7ZyycklgifJOHbYRvyDQmWUujRJnwYyGy+Sum JevCrB87dnWNhb8M0O0GT4tNq5puPKAOTBx/NWjlY3zrn08iJy3FoNRJ4 w10fVfpoGZosOql5VJwfd1LJrpRIUpcb8g2vzj9oj5qfu/iyuHppP1IFX Rz8EXX1mzInlTaTyCQXAtVFbL8ngzqR3vl1JQSKr7dL9jfSareA2eugUO VnIiM2kqbtmRS0bYOZOlJj3s0fNIhCIu+TqV2sJMfBwevOkdj9fgrR49D WCA13oIaiCEpfzipjqrcHuyMbcJBYBkIwKOp60JRMeQTFFHY5C8OUzsQJ w==; IronPort-SDR: O3DxDBNcXs8k9FMnGdLwSmpmYKVE74bN/nFdVG+qcBI3wF+SMnoV3GEysKljIWMIjC41rDf+yB Utk3rMF1BtVFY96ghE/9txZatBpUGkvD166vsIqLXQg2XvBvouCuCLOJcCTJEqJGDYKSu6gsaJ R24O7PqUf1CwT31CI9IF3bsd1tpAwmZnDT97nZbYLydUuob/CU7QNKENJhRPS22uj5Yf598+AZ LycKsfVszi9nwsVY4sF4cojIPtu2EuDFh/LI99QpzfEwP+Y7k1l2lwHFB5rVOxQYF6quLwBg1s 1nGz23sMOLw7HO4DHKzSuvY6 X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="147590593" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 06:41:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 06:41:53 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 06:41:51 -0700 From: Tudor Ambarus To: , CC: , , , , , "Tudor Ambarus" Subject: [PATCH v2 1/2] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Date: Fri, 17 Dec 2021 15:41:49 +0200 Message-ID: <20211217134150.497731-1-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Soft Reset and Rescue Sequence Support is defined in BFPT_DWORD(16) starting with JESD216A. The first version of SFDP, JESD216 (April 2011), defines just the first 9 BFPT DWORDS, thus it does not contain information about the Software Reset and Rescue Support. Since this support can not be discovered by parsing the first SFDP version, introduce a flash_info fixup_flag that will be used either by flashes that define JESD216 (April 2011) or by flashes that do not define SFDP at all. In case a flash defines BFPT_DWORD(16) but with wrong values, one should instead use a post_bfpt() hook and set SNOR_F_SOFT_RESET. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- v2: collect R-b drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 2e21d5ac0e2d..32d80fdaa2a2 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2699,6 +2699,9 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; + + if (fixup_flags & SPI_NOR_SOFT_RESET) + nor->flags |= SNOR_F_SOFT_RESET; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2afb610853a9..70c6bb7f5f04 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -373,6 +373,8 @@ struct spi_nor_fixups { * memory size above 128Mib. * SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode * via a volatile bit. + * SPI_NOR_SOFT_RESET: flash supports software reset enable, reset + * sequence. * @mfr_flags: manufacturer private flags. Used in the manufacturer fixup * hooks to differentiate support between flashes of the same * manufacturer. @@ -416,6 +418,7 @@ struct flash_info { u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1) +#define SPI_NOR_SOFT_RESET BIT(2) u8 mfr_flags; -- 2.25.1