From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE392C433EF for ; Wed, 19 Jan 2022 07:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351886AbiASHIW (ORCPT ); Wed, 19 Jan 2022 02:08:22 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351897AbiASHIS (ORCPT ); Wed, 19 Jan 2022 02:08:18 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:13 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback Date: Wed, 19 Jan 2022 15:08:08 +0800 Message-ID: <20220119070809.15563-4-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Due to some chips may use different registers and offset, provide a set trigger type call back. Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index eefe15e1b3a6..b511f9532adc 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -55,6 +55,8 @@ struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl, + unsigned int idx, u32 val); }; struct meson_gpio_irq_params { @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, */ type &= IRQ_TYPE_SENSE_MASK; + /* Some controllers may have different calculation method*/ + if (params->ops.gpio_irq_sel_type) { + params->ops.gpio_irq_sel_type(ctl, idx, type); + return 0; + } + /* * New controller support EDGE_BOTH trigger. This setting takes * precedence over the other edge/polarity settings -- 2.34.1