From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12FF4C433F5 for ; Wed, 19 Jan 2022 07:08:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351946AbiASHI1 (ORCPT ); Wed, 19 Jan 2022 02:08:27 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351902AbiASHIU (ORCPT ); Wed, 19 Jan 2022 02:08:20 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:13 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: [PATCH v2 4/4] irqchip/meson-gpio: Add support for meson s4 SoCs Date: Wed, 19 Jan 2022 15:08:09 +0800 Message-ID: <20220119070809.15563-5-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The meson s4 SoCs support 12 gpio irq lines compared with previous serial chips and have something different, details are as below. IRQ Number: - 80:68 13 pins on bank Z - 67:48 20 pins on bank X - 47:36 12 pins on bank H - 35:24 12 pins on bank D - 23:22 2 pins on bank E - 21:14 8 pins on bank C - 13:0 13 pins on bank B Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index b511f9532adc..896201d2f01f 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -42,6 +42,9 @@ #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) +/* Used for s4 chips */ +#define REG_EDGE_POL_S4 0x1c + struct meson_gpio_irq_controller; static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); @@ -50,6 +53,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); +static void meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl, + unsigned int idx, u32 val); struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, @@ -95,6 +100,20 @@ struct meson_gpio_irq_params { .pin_sel_mask = 0x7f, \ .nr_channels = 8, \ +#define INIT_MESON_S4_COMMON_DATA(irqs) \ + .nr_hwirq = irqs, \ + .ops = { \ + .gpio_irq_init = meson_a1_gpio_irq_init, \ + .gpio_irq_sel_pin = meson_a1_gpio_irq_sel_pin, \ + .gpio_irq_sel_type = meson_s4_gpio_irq_sel_type,\ + }, \ + .support_edge_both = true, \ + .edge_both_offset = 0, \ + .edge_single_offset = 12, \ + .pol_low_offset = 0, \ + .pin_sel_mask = 0xff, \ + .nr_channels = 12, \ + static const struct meson_gpio_irq_params meson8_params = { INIT_MESON8_COMMON_DATA(134) }; @@ -125,6 +144,10 @@ static const struct meson_gpio_irq_params a1_params = { INIT_MESON_A1_COMMON_DATA(62) }; +static const struct meson_gpio_irq_params s4_params = { + INIT_MESON_S4_COMMON_DATA(82) +}; + static const struct of_device_id meson_irq_gpio_matches[] = { { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, @@ -134,6 +157,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = { { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params }, { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params }, { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params }, + { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params }, { } }; @@ -200,6 +224,46 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); } +/* + * gpio irq relative registers for s4 + * -PADCTRL_GPIO_IRQ_CTRL0 + * bit[31]: enable/disable all the irq lines + * bit[12-23]: single edge trigger + * bit[0-11]: polarity trigger + * + * -PADCTRL_GPIO_IRQ_CTRL[X] + * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2 + * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1 + * where X = 1-6 + * + * -PADCTRL_GPIO_IRQ_CTRL[7] + * bit[0-11]: both edge trigger + */ +static void +meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl, + unsigned int idx, unsigned int type) +{ + unsigned int val = 0; + + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0); + + if (type == IRQ_TYPE_EDGE_BOTH) { + val |= BIT(ctl->params->edge_both_offset + idx); + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, + BIT(ctl->params->edge_both_offset + idx), val); + return; + } + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) + val |= BIT(ctl->params->pol_low_offset + idx); + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + val |= BIT(ctl->params->edge_single_offset + idx); + + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, + BIT(idx) | BIT(12 + idx), val); +}; + static int meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, unsigned long hwirq, -- 2.34.1