[RFC 2/3] soc: imx: make i.MX8MN BLK CTRL a separate driver

[Abel Vesa <abel.vesa@nxp.com>]

The imx8m-blk-ctrl driver was increasing in size with every new BLK CTRL
addition for every SoC. Lets split the SoC specific parts into separate
drivers. Do that for i.MX8MN now.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 drivers/soc/imx/Kconfig           |   7 +++
 drivers/soc/imx/Makefile          |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c  |  93 ---------------------------
 drivers/soc/imx/imx8mn-blk-ctrl.c | 101 ++++++++++++++++++++++++++++++
 4 files changed, 109 insertions(+), 93 deletions(-)
 create mode 100644 drivers/soc/imx/imx8mn-blk-ctrl.c

diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig
index b0cc53f3fc2c..8a3e0920b022 100644
--- a/drivers/soc/imx/Kconfig
+++ b/drivers/soc/imx/Kconfig
@@ -27,4 +27,11 @@ config SOC_IMX8MM_BLK_CTRL
 	  If you say yes here you get support for the NXP i.MX8MM BLK CTRL
 	  support.
 
+config SOC_IMX8MN_BLK_CTRL
+	bool "i.MX8MN SoC BLK CTRL support"
+	depends on SOC_IMX8M
+	help
+	  If you say yes here you get support for the NXP i.MX8MN BLK CTRL
+	  support.
+
 endmenu
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 06c2970e6308..f5243bc5f08f 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
 obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
 obj-$(CONFIG_SOC_IMX8MM_BLK_CTRL) += imx8mm-blk-ctrl.o
+obj-$(CONFIG_SOC_IMX8MN_BLK_CTRL) += imx8mn-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 599b2a9a38bb..ebdb044c6afa 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -6,8 +6,6 @@
 
 #include <linux/of_device.h>
 
-#include <dt-bindings/power/imx8mn-power.h>
-
 #include "imx8m-blk-ctrl.h"
 
 static inline struct imx8m_blk_ctrl_domain *
@@ -322,94 +320,3 @@ static int imx8m_blk_ctrl_resume(struct device *dev)
 const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
 	SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume)
 };
-
-static int imx8mn_disp_power_notifier(struct notifier_block *nb,
-				      unsigned long action, void *data)
-{
-	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
-						 power_nb);
-
-	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
-		return NOTIFY_OK;
-
-	/* Enable bus clock and deassert bus reset */
-	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
-	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
-
-	/*
-	 * On power up we have no software backchannel to the GPC to
-	 * wait for the ADB handshake to happen, so we just delay for a
-	 * bit. On power down the GPC driver waits for the handshake.
-	 */
-	if (action == GENPD_NOTIFY_ON)
-		udelay(5);
-
-
-	return NOTIFY_OK;
-}
-
-static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
-	[IMX8MN_DISPBLK_PD_MIPI_DSI] = {
-		.name = "dispblk-mipi-dsi",
-		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
-		.num_clks = 2,
-		.gpc_name = "mipi-dsi",
-		.rst_mask = BIT(0) | BIT(1),
-		.clk_mask = BIT(0) | BIT(1),
-		.mipi_phy_rst_mask = BIT(17),
-	},
-	[IMX8MN_DISPBLK_PD_MIPI_CSI] = {
-		.name = "dispblk-mipi-csi",
-		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
-		.num_clks = 2,
-		.gpc_name = "mipi-csi",
-		.rst_mask = BIT(2) | BIT(3),
-		.clk_mask = BIT(2) | BIT(3),
-		.mipi_phy_rst_mask = BIT(16),
-	},
-	[IMX8MN_DISPBLK_PD_LCDIF] = {
-		.name = "dispblk-lcdif",
-		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
-		.num_clks = 3,
-		.gpc_name = "lcdif",
-		.rst_mask = BIT(4) | BIT(5),
-		.clk_mask = BIT(4) | BIT(5),
-	},
-	[IMX8MN_DISPBLK_PD_ISI] = {
-		.name = "dispblk-isi",
-		.clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
-						"disp_apb_root"},
-		.num_clks = 4,
-		.gpc_name = "isi",
-		.rst_mask = BIT(6) | BIT(7),
-		.clk_mask = BIT(6) | BIT(7),
-	},
-};
-
-static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
-	.max_reg = 0x84,
-	.power_notifier_fn = imx8mn_disp_power_notifier,
-	.domains = imx8mn_disp_blk_ctl_domain_data,
-	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
-};
-
-static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
-	{
-		.compatible = "fsl,imx8mn-disp-blk-ctrl",
-		.data = &imx8mn_disp_blk_ctl_dev_data
-	}, {
-		/* Sentinel */
-	}
-};
-MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
-
-static struct platform_driver imx8m_blk_ctrl_driver = {
-	.probe = imx8m_blk_ctrl_probe,
-	.remove = imx8m_blk_ctrl_remove,
-	.driver = {
-		.name = "imx8m-blk-ctrl",
-		.pm = &imx8m_blk_ctrl_pm_ops,
-		.of_match_table = imx8m_blk_ctrl_of_match,
-	},
-};
-module_platform_driver(imx8m_blk_ctrl_driver);
diff --git a/drivers/soc/imx/imx8mn-blk-ctrl.c b/drivers/soc/imx/imx8mn-blk-ctrl.c
new file mode 100644
index 000000000000..20f53cd4e387
--- /dev/null
+++ b/drivers/soc/imx/imx8mn-blk-ctrl.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ * Copyright 2022 NXP, Abel Vesa <abel.vesa@nxp.com>
+ */
+
+#include <dt-bindings/power/imx8mn-power.h>
+
+#include "imx8m-blk-ctrl.h"
+
+static int imx8mn_disp_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
+	[IMX8MN_DISPBLK_PD_MIPI_DSI] = {
+		.name = "dispblk-mipi-dsi",
+		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi",
+		.rst_mask = BIT(0) | BIT(1),
+		.clk_mask = BIT(0) | BIT(1),
+		.mipi_phy_rst_mask = BIT(17),
+	},
+	[IMX8MN_DISPBLK_PD_MIPI_CSI] = {
+		.name = "dispblk-mipi-csi",
+		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi",
+		.rst_mask = BIT(2) | BIT(3),
+		.clk_mask = BIT(2) | BIT(3),
+		.mipi_phy_rst_mask = BIT(16),
+	},
+	[IMX8MN_DISPBLK_PD_LCDIF] = {
+		.name = "dispblk-lcdif",
+		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
+		.num_clks = 3,
+		.gpc_name = "lcdif",
+		.rst_mask = BIT(4) | BIT(5),
+		.clk_mask = BIT(4) | BIT(5),
+	},
+	[IMX8MN_DISPBLK_PD_ISI] = {
+		.name = "dispblk-isi",
+		.clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
+						"disp_apb_root"},
+		.num_clks = 4,
+		.gpc_name = "isi",
+		.rst_mask = BIT(6) | BIT(7),
+		.clk_mask = BIT(6) | BIT(7),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
+	.max_reg = 0x84,
+	.power_notifier_fn = imx8mn_disp_power_notifier,
+	.domains = imx8mn_disp_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
+};
+
+static const struct of_device_id imx8mn_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mn-disp-blk-ctrl",
+		.data = &imx8mn_disp_blk_ctl_dev_data
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8mn_blk_ctrl_of_match);
+
+static struct platform_driver imx8mn_blk_ctrl_driver = {
+	.probe = imx8m_blk_ctrl_probe,
+	.remove = imx8m_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8mn-blk-ctrl",
+		.pm = &imx8m_blk_ctrl_pm_ops,
+		.of_match_table = imx8mn_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8mn_blk_ctrl_driver);
-- 
2.31.1