From: Sean Christopherson <seanjc@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Zeng Guang <guang.zeng@intel.com>, Chao Gao <chao.gao@intel.com>,
Maxim Levitsky <mlevitsk@redhat.com>
Subject: [PATCH 02/11] KVM: VMX: Handle APIC-write offset wrangling in VMX code
Date: Fri, 4 Feb 2022 21:41:56 +0000 [thread overview]
Message-ID: <20220204214205.3306634-3-seanjc@google.com> (raw)
In-Reply-To: <20220204214205.3306634-1-seanjc@google.com>
Move the vAPIC offset adjustments done in the APIC-write trap path from
common x86 to VMX in anticipation of using the nodecode path for SVM's
AVIC. The adjustment reflects hardware behavior, i.e. it's technically a
property of VMX, no common x86. SVM's AVIC behavior is identical, so
it's a bit of a moot point, the goal is purely to make it easier to
understand why the adjustment is ok.
No functional change intended.
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 3 ---
arch/x86/kvm/vmx/vmx.c | 11 +++++++++--
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 4662469240bc..fbce455a9d17 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2188,9 +2188,6 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
{
u32 val = 0;
- /* hw has done the conditional check and inst decode */
- offset &= 0xff0;
-
kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
/* TODO: optimize to just emulate side effect w/o one more write */
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index b1165bb13a5a..1b135473677b 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -5302,9 +5302,16 @@ static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
static int handle_apic_write(struct kvm_vcpu *vcpu)
{
unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
- u32 offset = exit_qualification & 0xfff;
- /* APIC-write VM exit is trap-like and thus no need to adjust IP */
+ /*
+ * APIC-write VM-Exit is trap-like, KVM doesn't need to advance RIP and
+ * hardware has done any necessary aliasing, offset adjustments, etc...
+ * for the access. I.e. the correct value has already been written to
+ * the vAPIC page for the correct 16-byte chunk. KVM needs only to
+ * retrieve the register value and emulate the access.
+ */
+ u32 offset = exit_qualification & 0xff0;
+
kvm_apic_write_nodecode(vcpu, offset);
return 1;
}
--
2.35.0.263.gb82422642f-goog
next prev parent reply other threads:[~2022-02-04 21:42 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-04 21:41 [PATCH 00/11] KVM: x86: Prep work for VMX IPI virtualization Sean Christopherson
2022-02-04 21:41 ` [PATCH 01/11] Revert "svm: Add warning message for AVIC IPI invalid target" Sean Christopherson
2022-02-07 16:44 ` Paolo Bonzini
2022-02-04 21:41 ` Sean Christopherson [this message]
2022-02-15 2:22 ` [PATCH 02/11] KVM: VMX: Handle APIC-write offset wrangling in VMX code Chao Gao
2022-02-15 16:30 ` Sean Christopherson
2022-02-04 21:41 ` [PATCH 03/11] KVM: x86: Use "raw" APIC register read for handling APIC-write VM-Exit Sean Christopherson
2022-02-04 21:41 ` [PATCH 04/11] KVM: SVM: Use common kvm_apic_write_nodecode() for AVIC write traps Sean Christopherson
2022-02-04 23:14 ` kernel test robot
2022-02-07 16:16 ` Sean Christopherson
2022-02-04 21:41 ` [PATCH 05/11] KVM: SVM: Don't rewrite guest ICR on AVIC IPI virtualization failure Sean Christopherson
2022-02-04 21:42 ` [PATCH 06/11] KVM: x86: WARN if KVM emulates an IPI without clearing the BUSY flag Sean Christopherson
2022-02-04 21:42 ` [PATCH 07/11] KVM: x86: Make kvm_lapic_reg_{read,write}() static Sean Christopherson
2022-02-04 21:42 ` [PATCH 08/11] KVM: x86: Add helpers to handle 64-bit APIC MSR read/writes Sean Christopherson
2022-02-04 21:42 ` [PATCH 09/11] KVM: x86: Treat x2APIC's ICR as a 64-bit register, not two 32-bit regs Sean Christopherson
2022-02-15 3:27 ` Chao Gao
2022-02-15 16:40 ` Sean Christopherson
2022-02-04 21:42 ` [PATCH 10/11] KVM: x86: Make kvm_lapic_set_reg() a "private" xAPIC helper Sean Christopherson
2022-02-04 21:42 ` [PATCH 11/11] KVM: selftests: Add test to verify KVM handles x2APIC ICR=>ICR2 dance Sean Christopherson
2022-02-24 14:58 ` [PATCH 00/11] KVM: x86: Prep work for VMX IPI virtualization Paolo Bonzini
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