From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EB09C4167D for ; Mon, 7 Feb 2022 13:13:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353848AbiBGNMY (ORCPT ); Mon, 7 Feb 2022 08:12:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1445378AbiBGMmC (ORCPT ); Mon, 7 Feb 2022 07:42:02 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40597E0321DD for ; Mon, 7 Feb 2022 04:33:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644237211; x=1675773211; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=x6kFVrzT05XFotdvtiT0qifyAXqqSEHdTPezDSU7rR8=; b=IA3ugXAmGTNY+s33704DvbybAOE4u7SFDXBSSy6J4RbFtRdGukYN5Zhi dc5JVkLKVPw+qblq6ac8h4qkBe/m7sooZFPKvSgRLJFZVDKJ09DE2kY/c ht5P5HAhs5lWeA7JYT/VmxXbqgXfopqary0wkevQiNcbXWL0mG20pddl4 lAhxeQIs6BMeD64skdRuEEF/Rj97JROIVZ3DBhyXZCJHIVyQCmjaoNwXA RIr8vR3Q9ShumJ9khH0+ZJB/wBA2Y8FtgInZvi6iUsYlDslBpRUA461Ti rFLcmwJhZHkLnjhItMH+FowAOvj90T6WCzcTe2cMBcLZFDjRJfX+t6Fe6 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10250"; a="247538984" X-IronPort-AV: E=Sophos;i="5.88,349,1635231600"; d="scan'208";a="247538984" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2022 04:33:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,349,1635231600"; d="scan'208";a="484406335" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga006.jf.intel.com with ESMTP; 07 Feb 2022 04:33:28 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 57F393ED; Mon, 7 Feb 2022 14:33:43 +0200 (EET) From: Andy Shevchenko To: Peter Zijlstra , linux-kernel@vger.kernel.org Cc: Andrew Morton , Andy Shevchenko , =?UTF-8?q?Jan=20D=C4=85bro=C5=9B?= Subject: [PATCH v2 1/1] bitfield: Add explicit inclusions to the example Date: Mon, 7 Feb 2022 14:33:41 +0200 Message-Id: <20220207123341.47533-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It's not obvious that bitfield.h doesn't guarantee the bits.h inclusion and the example in the former is confusing. Some developers think that it's okay to just include bitfield.h to get it working. Change example to explicitly include necessary headers in order to avoid confusion. Fixes: 3e9b3112ec74 ("add basic register-field manipulation macros") Depends-on: 8bd9cb51daac ("locking/atomics, asm-generic: Move some macros from to a new file") Reported-by: Jan Dąbroś Signed-off-by: Andy Shevchenko --- v2: used full paths include/linux/bitfield.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 6093fa6db260..c9be1657f03d 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -19,6 +19,9 @@ * * Example: * + * #include + * #include + * * #define REG_FIELD_A GENMASK(6, 0) * #define REG_FIELD_B BIT(7) * #define REG_FIELD_C GENMASK(15, 8) -- 2.34.1