From: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
bhelgaas@google.com, logang@deltatee.com,
michael.j.ruhl@intel.com
Cc: dan.j.williams@intel.com
Subject: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information
Date: Wed, 9 Feb 2022 11:28:01 -0500 [thread overview]
Message-ID: <20220209162801.7647-1-michael.j.ruhl@intel.com> (raw)
In order to do P2P communication the bridge ID of the platform
must be in the P2P device table.
Update the P2P device table with a device id for the 3rd Gen
Intel Xeon Scalable Processors.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
---
drivers/pci/p2pdma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 1015274bd2fe..30b1df3c9d2f 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
{PCI_VENDOR_ID_INTEL, 0x2032, 0},
{PCI_VENDOR_ID_INTEL, 0x2033, 0},
{PCI_VENDOR_ID_INTEL, 0x2020, 0},
+ {PCI_VENDOR_ID_INTEL, 0x09a2, 0},
{}
};
--
2.31.1
next reply other threads:[~2022-02-09 16:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 16:28 Michael J. Ruhl [this message]
2022-02-25 15:49 ` Ruhl, Michael J
2022-02-25 17:09 ` Bjorn Helgaas
2022-02-25 19:14 ` Ruhl, Michael J
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