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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT019.mail.protection.outlook.com (10.13.176.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4975.11 via Frontend Transport; Fri, 11 Feb 2022 21:06:09 +0000 Received: from localhost.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Fri, 11 Feb 2022 15:06:07 -0600 From: Mario Limonciello To: Borislav Petkov , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" CC: Kees Cook , Thomas Lendacky , , Martin Fernandez , , "Brijesh Singh" , Mario Limonciello Subject: [PATCH v2 3/4] x86/cpu: clear SME features when not in use Date: Fri, 11 Feb 2022 15:02:54 -0600 Message-ID: <20220211210255.9820-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220211210255.9820-1-mario.limonciello@amd.com> References: <20220211210255.9820-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d7d0b3fb-731d-426a-909a-08d9eda253f4 X-MS-TrafficTypeDiagnostic: BL1PR12MB5271:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2022 21:06:09.7876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d7d0b3fb-731d-426a-909a-08d9eda253f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5271 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently the SME CPU feature flag is reflective of whether the CPU supports the features but not whether they have been activated by the kernel. Change this around to clear the features if the kernel is not using them so userspace can determine if they are available and in use from `/proc/cpuinfo`. As the feature flag is now cleared on systems that SME isn't active use CPUID 0x8000001f to confirm SME availability before calling `native_wbinvd`. Signed-off-by: Mario Limonciello --- A concern was raised whether the assembly generated from stop_this_cpu is still safe. Here is the assembly from compiling with this patch: 00000000000011d0 : 11d0: e8 00 00 00 00 call 11d5 11d5: 55 push %rbp 11d6: 48 89 e5 mov %rsp,%rbp 11d9: 41 54 push %r12 11db: 53 push %rbx 11dc: 48 83 ec 18 sub $0x18,%rsp 11e0: 65 48 8b 04 25 28 00 mov %gs:0x28,%rax 11e7: 00 00 11e9: 48 89 45 e8 mov %rax,-0x18(%rbp) 11ed: 31 c0 xor %eax,%eax 11ef: ff 14 25 00 00 00 00 call *0x0 11f6: e8 00 00 00 00 call 11fb 11fb: 31 f6 xor %esi,%esi 11fd: 48 c7 c3 00 00 00 00 mov $0x0,%rbx 1204: 89 c7 mov %eax,%edi 1206: e8 00 00 00 00 call 120b 120b: e8 00 00 00 00 call 1210 1210: e8 00 00 00 00 call 1215 1215: 41 89 c4 mov %eax,%r12d 1218: 3d ff 1f 00 00 cmp $0x1fff,%eax 121d: 77 49 ja 1268 121f: 4a 03 1c e5 00 00 00 add 0x0(,%r12,8),%rbx 1226: 00 1227: 48 89 df mov %rbx,%rdi 122a: e8 00 00 00 00 call 122f 122f: c7 45 d8 1f 00 00 80 movl $0x8000001f,-0x28(%rbp) 1236: 48 8d 7d d8 lea -0x28(%rbp),%rdi 123a: 48 8d 75 dc lea -0x24(%rbp),%rsi 123e: c7 45 e0 00 00 00 00 movl $0x0,-0x20(%rbp) 1245: 48 8d 55 e0 lea -0x20(%rbp),%rdx 1249: 48 8d 4d e4 lea -0x1c(%rbp),%rcx 124d: ff 14 25 00 00 00 00 call *0x0 1254: f6 45 d8 01 testb $0x1,-0x28(%rbp) 1258: 74 02 je 125c 125a: 0f 09 wbinvd 125c: eb 07 jmp 1265 125e: 0f 00 2d 00 00 00 00 verw 0x0(%rip) # 1265 1265: f4 hlt 1266: eb f4 jmp 125c 1268: 4c 89 e6 mov %r12,%rsi 126b: 48 c7 c7 00 00 00 00 mov $0x0,%rdi 1272: e8 00 00 00 00 call 1277 1277: eb a6 jmp 121f 1279: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) arch/x86/kernel/cpu/amd.c | 3 +++ arch/x86/kernel/process.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 4edb6f0f628c..9cea774344cb 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -607,6 +607,9 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) if (IS_ENABLED(CONFIG_X86_32)) goto clear_all; + if (!sme_me_mask) + goto clear_all; + rdmsrl(MSR_K7_HWCR, msr); if (!(msr & MSR_K7_HWCR_SMMLOCK)) goto clear_sev; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 81d8ef036637..e131d71b3cae 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -765,8 +765,11 @@ void stop_this_cpu(void *dummy) * without the encryption bit, they don't race each other when flushed * and potentially end up with the wrong entry being committed to * memory. + * + * Test the CPUID bit directly because the machine might've cleared + * X86_FEATURE_SME due to cmdline options. */ - if (boot_cpu_has(X86_FEATURE_SME)) + if (cpuid_eax(0x8000001f) & BIT(0)) native_wbinvd(); for (;;) { /* -- 2.34.1