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(adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:21 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 0/6] Provide a fraemework for RISC-V ISA extensions Date: Tue, 22 Feb 2022 12:48:05 -0800 Message-Id: <20220222204811.2281949-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series implements a generic framework to parse multi-letter ISA extensions. This series is based on Tsukasa's v3 isa extension improvement series[1]. I have fixed few bugs and improved comments from that series (PATCH1-3). I have not used PATCH 4 from that series as we are not using ISA extension versioning as of now. We can add that later if required. PATCH 4 allows the probing of multi-letter extensions via a macro. It continues to use the common isa extensions between all the harts. Thus hetergenous hart systems will only see the common ISA extensions. PATCH 6 improves the /proc/cpuinfo interface for the available ISA extensions via /proc/cpuinfo. Here is the example output of /proc/cpuinfo: (with debug patches in Qemu and Linux kernel) # cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdch isa-ext : svpbmt svnapot svinval mmu : sv48 processor : 1 hart : 1 isa : rv64imafdch isa-ext : svpbmt svnapot svinval mmu : sv48 processor : 2 hart : 2 isa : rv64imafdch isa-ext : svpbmt svnapot svinval mmu : sv48 processor : 3 hart : 3 isa : rv64imafdch isa-ext : svpbmt svnapot svinval mmu : sv48 Anybody adding support for any new multi-letter extensions should add an entry to the riscv_isa_ext_id and the isa extension array. E.g. The patch[2] adds the support for various ISA extensions. [1] https://lore.kernel.org/all/0f568515-a05e-8204-aae3-035975af3ee8@irq.a4lg.com/T/ [2] https://github.com/atishp04/linux/commit/e9e240c9a854dceb434ceb53bdbe82a657bee5f2 Changes from v4->v5: 1. Improved the /proc/cpuinfo to include only valid & enabled extensions 2. Improved the multi-letter parsing by skipping the 'su' modes generated in Qemu as suggested by Tsukasa. Changes from v3->v4: 1. Changed temporary variable for current hart isa to a bitmap 2. Added reviewed-by tags. 3. Improved comments Changes from v2->v3: 1. Updated comments to mark clearly a fix required for Qemu only. 2. Fixed a bug where the 1st multi-letter extension can be present without _ 3. Added Tested by tags. Changes from v1->v2: 1. Instead of adding a separate DT property use the riscv,isa property. 2. Based on Tsukasa's v3 isa extension improvement series. Atish Patra (3): RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Improve /proc/cpuinfo output for ISA extensions Tsukasa OI (3): RISC-V: Correctly print supported extensions RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Extract multi-letter extension names from "riscv, isa" arch/riscv/include/asm/hwcap.h | 25 +++++++ arch/riscv/kernel/cpu.c | 51 ++++++++++++- arch/riscv/kernel/cpufeature.c | 130 +++++++++++++++++++++++++++------ 3 files changed, 183 insertions(+), 23 deletions(-) -- 2.30.2